Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2001-04-02
2002-10-01
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S191000, C365S189050
Reexamination Certificate
active
06459628
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to memory devices and, more particularly, to a system and method to facilitate stabilization of reference voltage signals in memory devices.
BACKGROUND OF THE INVENTION
Flash memory is a type of electronic memory media which can be rewritten and hold its content without power. Flash memory devices generally have life spans from 100K to 1M write cycles. Unlike dynamic random access memory (DRAM) and static random access memory (SRAM) memory chips, in which a single byte can be erased, flash memory is typically erased and written in fixed multi-bit blocks or sectors. Evolving out of electrically erasable read only memory (EEPROM) chip technology, which can be erased in place, flash memory is less expensive and denser. This new category of EEPROMs has emerged as an important non-volatile memory which combines the advantages of EPROM density with EEPROM electrical erasability.
Conventional flash memories are constructed in a cell structure wherein a single bit of information is stored in each cell. In such single bit memory architectures, each cell typically includes a metal oxide semiconductor (MOS) transistor structure having a source, a drain, and a channel in a substrate or P-well, as well as a stacked gate structure overlying the channel. The stacked gate may further include a thin gate dielectric layer (sometimes referred to as a tunnel oxide) formed on the surface of the P-well. The stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. The interpoly dielectric layer is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate overlies the interpoly dielectric layer.
The control gate is connected to a word line associated with a row of such cells to form sectors of such cells in a typical NOR configuration. In addition, the drain regions of the cells are connected together by a conductive bit line. The channel of the cell conducts current between the source and the drain in accordance with an electric field developed in the channel by the stacked gate structure. In the NOR configuration, each drain terminal of the transistors within a single column is connected to the same bit line. In addition, each flash cell associated with a given bit line has its stacked gate terminal coupled to a different word line, while all the flash cells in the array have their source terminals coupled to a common source terminal. In operation, individual flash cells are addressed via the respective bit line and word line using peripheral decoder and control circuitry for programming (writing), reading, or erasing functions.
Such a single bit stacked gate flash memory cell is programmed by applying a relatively high voltage to the control gate and connecting the source to ground and the drain to a predetermined potential above the source.
By way of example, flash memories have a typical operating voltage of about 5 volts. A reference voltage, however, is usually required for programming and erase operations in a flash memory. The reference voltage usually is in the range of about 1.29 to 1.31 volts, but can be higher. When the reference voltage is enabled, it ramps up to a desired level, taking time to stabilize. If programming occurs prior to the reference voltage sufficiently stabilizing, there is an increased likelihood of errors during programming.
During a programming operation, electrons are injected onto the floating gate by applying a regulated voltage signal based on the reference voltage to the control gate and about one-half the regulated voltage to the drain region while the source region is grounded. A resulting high electric field across the tunnel oxide leads to a phenomena called “Fowler-Nordheim” tunneling. During this process, electrons in the core cell channel region tunnel through the gate oxide into the floating gate and become trapped in the floating gate since the interpoly dielectric and the tunnel oxide surround the floating gate. As a result of the trapped electrons, the threshold voltage of the cell increases. The change in the threshold voltage (and thereby the channel conductance) of the cell created by the trapped electrons is what causes the cell to be programmed. In order to generate the reference voltages required to program and erase memory cells, a reference voltage circuit ramps up to a predetermined voltage.
In order to erase a typical single bit stacked gate flash memory cell, a relatively high voltage is applied to the source, and the control gate is held at a negative potential, while the drain is allowed to float. Under these conditions, a strong electric field is developed across the tunnel oxide between the floating gate and the source. The electrons that are trapped in the floating gate flow toward and cluster at the portion of the floating gate overlying the source region and are extracted from the floating gate and into the source region by way of Fowler-Nordheim tunneling through the tunnel oxide. As the electrons are removed from the floating gate, the cell is erased.
In conventional single bit flash memory devices, erase verification is performed to determine whether each cell in a block or set of such cells has been properly erased. Current single bit erase verification methodologies provide for verification of bit or cell erasure, and application of supplemental erase pulses to to individual cells which fail the initial verification. Thereafter, the erased status of the cell is again verified, and the process continues until the cell or bit is successfully erased or the cell is marked as unusable.
SUMMARY
The present invention provides a system and related method to facilitate stabilization of a reference voltage signal in a memory device. A wait system is operative to provide a wait signal to delay performance of each operation relative the memory cell. The wait signal is operative to delay performance of at least one initial operation relative the memory cell during a given user mode by a first duration. After the initial wait signal, the wait signal is provided to delay performance of subsequent operations relative the memory cell during the given user mode by a second duration, which is less than the first duration. The initial, greater amount of initial delay enables a reference signal to sufficiently ramp up to a desired level at the beginning of a user mode so as to mitigate errors that could otherwise occur if the reference signal did not stabilize at its desired level.
In accordance with one particular aspect, the initial wait signal may be selectable so as to provide a selected amount of delay. For example, the wait system may include a selection system operative to receive a selection signal having at least two conditions. The selection signal is operative to select which of at least two signals having different associated durations is to be provided as the initial wait signal according to the condition of the selection signal. For example, in a case when the system is implemented as part of an integrated circuit, the selection system may include a metal option. The metal option may have two or more user-selectable conditions (e.g., different fixed voltage levels), each of which provides a different selection signal, thereby controlling which of the signals will be provided as the initial wait signal.
In accordance with another aspect of the present invention, the initial wait signal may be masked for the subsequent operations in the given user mode to be performed relative the memory cell. By masking the initial wait signal, subsequent wait signals during the given user mode may be provided so as to provide a lesser amount of delay for subsequent operations to be performed relative the memory cell.
REFERENCES:
patent: 5386385 (1995-01-01), Stephens, Jr.
patent: 5798974 (1998-08-01), Yamagata
patent: 5978275 (1999-11-01), Song et al.
patent: 5991851 (1999-11-01), Alwais et al.
paten
Bautista, Jr. Edward V.
Lee Weng Fook
Yachareni Santosh K.
Eschweiler & Associates LLC
Nelms David
Pham Ly Dny
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