System and method of forming a split-gate flash memory...

Details System and method of forming a split-gate flash memory... System and method of forming a split-gate flash memory...

2006-12-12

2006-12-12

Brewster, William M. (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S218000, C438S257000, C438S691000

Reexamination Certificate

active

07148098

ABSTRACT:
A method for forming a split-gate flash memory structure includes etching a first gate layer to form one or more floating gates and forming an isolation layer over the floating gates. An insulation layer is deposited over the isolation layer and planarized.

REFERENCES:
patent: 2001/0012662 (2001-08-01), Hsieh et al.
patent: 2003/0073276 (2003-04-01), Lin et al.
Stanley Wolf Ph.D. in Silicon Processing for the VLSI Era, vol. 2: Process Integration, Lattice Press, 1990, p. 194.
Rebecca Mih et al., “0.18 um Modular Triple Self-Aligned Embedded Split-gate Flash Memory”, 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 120-121.

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