System and method for testing pattern sensitive algorithms...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

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11202591

ABSTRACT:
A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.

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Stirniman, John P. et al., “Spatial filter models to describe IC lithographic behavior,” SPIE, vol. 3051, 0277-786X/97, pp. 469-478.

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