Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-04-12
2005-04-12
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S729000
Reexamination Certificate
active
06880118
ABSTRACT:
A source synchronous test methodology and apparatus. In one embodiment, an integrated circuit (IC) configured for source synchronous I/O transactions may be a device under test (DUT) and may be mounted to a load board for testing. The load board may be electrically coupled to a test system. The test system may shift first test data into a first IC on the load board. The first chip may then transmit the first test data through a source synchronous line, or a source synchronous link having a plurality of lines, to a second IC. Second test data produced responsive to the source synchronous transmission is then shifted from the second IC to the tester. The second test data is then analyzed. The analysis may comprise comparing the second data to expected data, and/or may also comprise analyzing the second data with respect to an eye window.
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Chen Cecilia T.
Fong Wai
Jong Jyh-Ming
Smith Brian L.
Yuan Leo
Kowert Robert C.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Sun Microsystems Inc.
Ton David
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