Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-04-22
2002-02-05
Tu, Christine T. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000
Reexamination Certificate
active
06345373
ABSTRACT:
IA. FIELD OF THE INVENTION
The present invention relates to testing systems, including testing of VLSI circuits. Specifically, the present invention relates to testing high-speed systems (including testing of high-speed VLSI circuit) using testers that are slower than the high-speed systems (VLSI circuits) that are tested. The present invention is embodied in a method for generating vectors to be used in a slow tester; in a method for testing VLSI devices using a slow tester; and a system for testing VLSI circuits comprising a slow tester.
IB. BACKGROUND OF THE INVENTION
It should be noted that the background description and the preferred embodiments are described with reference to VLSI circuits. However, it should be clear to a skilled artisan that the system and methods of the present invention can be used for testing in a system using a tester that operates at a speed no more than the speed of the system.
The operating speed of VLSI circuits is continuously increasing. Even small delay faults can cause VLSI circuits to malfunction. The temporal correctness of a circuit design can be ensured by subjecting the circuit to delay testing. To detect timing defects and test the performance of the circuit, pre-generated test vectors are applied to the circuit. These delay-testing vectors need to be applied to the circuit during a test at the circuit's intended operating speed. However, testers that are currently used in testing VLSI circuits are usually several times slower than the speed of the new VLSI designs.
As can be readily seen, a gap exists between the speed of the VLSI circuit to be tested and the speed of the tester used test the VLSI circuit. However, purchasing high-speed testers that operate at the speed of the new VLSI designs is expensive. The above-mentioned gap between the speed of the testers and high performance designs is unlikely to disappear in the foreseeable future. Therefore, it is important to find ways to test fast VLSI designs on slower testers.
The problem of testing high-speed circuits without high-speed testers has been discussed in conventional literature. See K. D. Wagner and E. J. McCluskey. Effect of Supply Voltage on Circuit Propagation Delay and Test Application.
Proc. of ICCAD
, pages 42-44, November 1985; S. Barton. Characterization of High-Speed (Above 500 MHz) Devices using Advanced ATE—Technique, Results and Device Problems.
Proc. of ITC
, pages 860-868, October 1989; L. Ackner and M. R. Barber. Frequency Enhancement of Digital VLSI Test Systems.
Proc. of ITC
, pages 444-451, October 1990; D. C. Keezer. Multiplexing Test System Channels for Data Rates Above 1 Gb/s.
Proc. of ITC
, pages 790-797, October 1990; H. Hao and E. J. McCluskey. Very Low Voltage Testing for Weak CMOS Logic ICs.
Proc. of ITC
, pages 275-284, October 1993, V. D. Agrawal, C.-J. Lin, P. W. Rutkowski, S. Wu, and Y. Zorian. Built-In Self-Test for Digital Integrated Circuits. AT~3T
Technical Journal
, 73:30-39, March 1994; J. A. Gasbarro and M. A. Horowitz. Techniques for Characterizing DRAMS with a 500 MHz Interface.
Proc. of ITC
, pages 516-525, October 1994, V. D. Agrawal and T. J. Chakraborty. High-Performance Circuit Testing with Slow-Speed Testers.
Proc. of ITC
, pages 302-310, October 1995; and D. Heidel et al. High Speed Serializing/De-Serializing Design-for-Test Method for evaluating a 1 GHz Microprocessor.
Proc. of ITC
, pages 234-238, October 1998.
Conventional strategies for testing high-speed VLSI circuits include:
tester pin multiplexing. See L. Ackner and M. R. Barber. Frequency Enhancement of Digital VLSI Test Systems.
Proc. of ITC
, pages 444-451, October 1990;
built-in self-test See V. D. Agrawal, C.-J. Lin, P. W. Rutkowski, S. Wu, and Y. Zorian. Built-In Self-Test for Digital Integrated Circuits. AT~3T Technical Journal, 73:30-39, March 1994;
use of a high-speed clock and shift registers. See D. C. Keezer. Multiplexing Test System Channels for Data Rates Above 1 Gb/s.
Proc. of ITC
, pages 790-797, October 1990;
use of special test fixtures. See S. Barton. Characterization of High-Speed (Above 500 MHz) Devices using Advanced ATE—Technique, Results and Device Problems.
Proc. of ITC
, pages 860-868, October 1989;
reducing the supply voltage. See K. D. Wagner and E. J. McCluskey. Effect of Supply Voltage on Circuit Propagation Delay and Test Application.
Proc. of ICCAD
, pages 42-44, November 1985 and See H. Hao and E. J. McCluskey. Very Low Voltage Testing for Weak CMOS Logic ICs.
Proc. of ITC
, pages 275-284, October 1993;
use of on-chip test circuitry for testing high bandwidth memories. See J. A. Gasbarro and M. A. Horowitz. Techniques for Characterizing DRAMS with a 500 MHz Interface.
Proc. of ITC
, pages 516-525, October 1994;
adding extra logic;. See V. D. Agrawal and T. J. Chakraborty. High-Performance Circuit Testing with Slow-Speed Testers.
Proc. of ITC
, pages 302-310, October 1995; and
serializing parallel circuit inputs and de-serializing circuit outputs. See D. Heidel et al. High Speed Serializing/De-Serializing Design-for-Test Method for evaluating a 1 GHz Microprocessor.
Proc. of ITC
, pages 234-238, October 1998.
Faults that result in a circuit not producing the correct functional results are called stuck-at faults. Faults that lead to increased delay in generating results are called delay faults. A series of vectors are applied in one or more clock cycles to get a circuit to a stage where it may generate a specific fault. A vector set is applied at one clock cycle after the initialization stage in an activation stage to actually generate the fault. The fault that may show up at a flip-flop or at one of the primary outputs is then transmitted out to be observed during a fault propagation stage, which may require one or more clock cycles and vectors.
Unlike conventional stuck-at fault test generation, test generation for delay faults is closely tied to the test application strategy. Therefore, prior to generating test vectors for delay faults, how the test vectors should be applied to the circuit needs to be determined. Two commonly used testing strategies for sequential circuits are slow-fast-slow strategy and at-speed strategy.
Slow-fast-slow testing strategy assumes that the vectors for initialization and propagation of the fault effect are applied at a slow speed. In such slow speeds up the circuit can be considered delay fault-free in these testing stages. See S. Devadas. Delay Test Generation for Synchronous Sequential Circuits.
Proc. of ITC
, pages 144-152, September 1989; P. Agrawal, V. D. Agrawal, and S. C. Seth. Generating Tests for Delay Faults in Nonscan Circuits. Design &1
Test of Computers
, pages 20-28, March 1993; and T. J. Chakraborty, V. D. Agrawal, and M. L. Bushnell. Delay Fault Models and Test Generation of Random Logic Sequential Circuits.
Proc. of DAC
, pages 453-457, June 1993. Activation of the fault in a slow-fast-slow strategy is performed by applying a fast clock. It should be noted that in the slow-fast-slow strategy, fast simply means that the clock during the activation stage is faster than that in the initialization and propagation stage. Such a fast clock, as discussed in subsequent sections related to at-speed strategies, does not operate at the speed of the circuit that is tested.
At-speed testing strategy assumes that the fault is initialized, activated and propagated under a fast clock. Unlike the fast clock in the slow-fast-slow, at-speed testing strategies have been proposed that assume that the inputs are applied and the outputs are observed at the rated speed of the circuits that are tested. See I. Pomeranz and S. M. Reddy. At-Speed Delay Testing of Synchronous Sequential Circuits.
Proc. of DAC
, pages 177-181, June 1992, K.-T. Cheng. Transition Fault Testing for Sequential Circuits.
Trans. on CAD
, 12(12):1971-1983, December 1993; and S. Bose, P. Agrawal, and V. D. Agrawal. A Rated-Clock Test Method for Path Delay Faults.
Trans. on VLSI
, 6(2):323-331, June 1998. However, the at-speed strategy mention above assumes that a high-speed tester is available. To differentiate be
Chakradhar Srimat T.
Cheng Kwang-Ting
Krstic Angela
Sughrue & Mion, PLLC
The University of California
Tu Christine T.
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