Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-09-28
2002-04-23
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S742000
Reexamination Certificate
active
06378097
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the field of testing microprocessors, and more particularly, to a system and method for testing a microprocessor with a test vector generator stored in on-chip memory.
BACKGROUND OF THE INVENTION
Testing microprocessors is a critical, yet expensive, step of the fabrication process. Microprocessors are formed on silicon wafers, which are very thin, round slices from a cylinder of silicon. Microscopic circuitry for multiple microprocessors is then formed on the silicon wafer. The fabrication must take place in a clean room, i.e., a chamber in which dust or other impurities are reduced to extremely low levels. Any unwanted impurities in the silicon wafer or in the circuitry of a microprocessor can cause it or parts of it to fail. Because a microprocessor may be only several millimeters or centimeters wide, and may comprise millions of transistors, it can be very difficult to test thoroughly. Furthermore, microprocessors are very fragile and easy to damage during the fabrication process. For example, a typical static charge built up as a person walks about normally can be about 10,000 volts, and a static discharge onto a microprocessor can destroy it with only around 5,000 volts.
After the microprocessor circuitry is added to the silicon wafer, the wafer is cut into sections, or die, each containing one microprocessor. Each die is then placed in a package made of a material such as plastic or ceramic. The package also includes electrical contacts which allow connection of the microprocessor inside the package to a circuit board or other electrical system. Since fabricating microprocessors is such an expensive process, they are typically tested at various stages, such as before and after packaging, to allow the earliest possible rejection of defective parts. After the post-packaging test, microprocessors are operated at extreme environmental conditions, or “burned-in,” and retested to eliminate those with latent defects which only occur after the microprocessor has been operated.
Microprocessors are generally tested on a parallel-pin tester, an extremely expensive machine with hundreds of electrical contacts and a very large amount of fast memory. Microprocessor instructions called test vectors are stored in the memory of the parallel-pin tester. Test cases, made up of sets of test vectors, are typically written by circuit designers in a time consuming and laborious process, and are therefore of widely varying quality depending upon the efforts and skill of those writing them. It is an extremely difficult task to produce test vectors which thoroughly test a highly complex circuit such as a microprocessor.
A microprocessor, either packaged or unpackaged, is connected to the parallel-pin tester and the test cases are executed in the microprocessor in order to detect failures.
Parallel-pin testers have several disadvantages. The amount of memory in a parallel-pin tester limits the number and size of test cases which can be executed on a microprocessor. Furthermore, the speed of the parallel-pin tester and its memory limit the speed at which the microprocessor can run during the test. Generally, the clock speed of the microprocessors must be slower than normal operating speed during testing on a parallel-pin tester, limiting the efficacy of the test.
Another major challenge of effectively testing microprocessors with a parallel pin tester is the difficulty of keeping the one or more core execution units in a microprocessor occupied and exercised. Microprocessors may have multiple core execution units which must be tested, but the external bandwidth is limited even with a large parallel pin tester. As a result, core execution units may be idle or only minimally exercised during some parallel pin testing.
The cost of parallel-pin testers limits the number that a fabricator can afford to purchase, thus the number of microprocessors that can be tested at one time is limited. This disadvantage is further compounded by the need to test the same microprocessor several times at various stages of fabrication.
A need therefore exists for a system and method of testing microprocessors which is less expensive, enabling simultaneous testing of a greater number of microprocessors. An additional need exists for a system and method of testing microprocessors that can be executed in the microprocessor at its normal operating speed. A further need exists for a system and method of testing microprocessors that more fully occupies and exercises the core execution units of a microprocessor.
SUMMARY
To assist in achieving the aforementioned needs, the inventors have devised a system and method for testing a microprocessor with a test vector generator stored in the microprocessor's internal memory.
A system for testing a microprocessor having features of the present invention comprises a microprocessor having one or more a core execution units, an internal memory, and a data port, and a relatively low cost tester having a data port which is connected to the microprocessor data port. The tester has a low cost interface such as a serial port. The tester may have memory which is relatively smaller and slower, therefore less expensive, than the memory required in a parallel pin tester.
A test vector generator program is transferred from the tester to the internal memory of the microprocessor for testing the microprocessor when it is executed by the core execution unit. The test vector generator program generates test vectors which are also stored in the internal memory, and which may then be executed by the core execution unit.
The microprocessor data port is generally a low cost interface such as a serial port. In a preferred embodiment, the serial interface may comprise a JTAG test interface. The test vector generator program and the generated test vectors may be executed by the core execution unit at the full clock speed of the microprocessor.
The present invention may also comprise a method for testing a microprocessor having a core execution unit, an internal memory and a data port, including providing a tester having a data port and a memory, and providing a test vector generator program in the memory of the tester. The method further includes connecting the microprocessor data port to the tester data port, transferring the test vector generator program from the tester through the tester data port to the internal memory through the microprocessor data port, and executing the test vector generator program in the core execution unit to generate test vectors.
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Dixon Daniel J.
Fin Brian P.
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