System and method for system-on-chip interconnect verification

Details System and method for system-on-chip interconnect verification System and method for system-on-chip interconnect verification

2011-01-04

2011-01-04

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S025000, C714S030000, C714S031000, C714S032000, C714S043000, C714S045000, C714S056000, C714S741000, C714S048000, C714S716000, C714S717000, C714S712000, C714S709000, C714S715000, C714S726000, C714S728000, C714S733000, C714S738000, C714S739000, C714S718000, C702S108000, C702S118000, C703S014000, C703S015000, C703S021000, C703S022000, C365S201000

Reexamination Certificate

active

07865789

ABSTRACT:
A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

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