4. Error detection/correction and fault detection/recovery
  5. Pulse or data error handling
  6. Digital logic testing

Jason M. Norman

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Assigning clock arrival time for noise reduction

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
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Circuit design verification using checkpointing

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
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Critical path redundant logic for mitigation of hardware...

Electronic digital logic circuitry – With test facilitating feature
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Data acknowledgment using impedance mismatching

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
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Fiber optic transmission lines on an SOC

Optical communications – Transmitter and receiver system – Plural stations
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Profile ID: LFUS-PAI-P-2271207

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