System and method for sign-off timing closure of a VLSI chip

Details System and method for sign-off timing closure of a VLSI chip System and method for sign-off timing closure of a VLSI chip

2007-02-28

2009-08-25

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07581201

ABSTRACT:
A method for performing timing optimization of a detail routed netlist, incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in a tightly coupled, incremental manner with minimal perturbations to the placement, routing, and asserted parasitic information. The method corrects violations in a placed and routed design of a VLSI circuit chip, where the design is represented by a netlist describing logical and physical characteristics of the design and by a corresponding timing graph, the method including the steps of: identifying violations in the design; iteratively eliminating the violations by incrementally transforming the logical and the physical characteristics of the design, incorporating in the design only legal placements and routes; and applying incremental timing to evaluate the transformations, and updating the existing timing graphs to reflect changes consisting of the legal placements and routes.

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U.S. Appl. No. 11/420,529, to Gregory M. Schaeffer et al., entitled, “Method for a Fast Incremental Calculation of the Impact of a Coupled Noise on Timing”, filed May 26, 2006.

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