Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-11-30
2003-09-09
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C702S118000, C714S742000
Reexamination Certificate
active
06618830
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The invention relates in general to the field of integrated circuits and more particularly to a system and method for pruning a bridging diagnostic list.
BACKGROUND OF THE INVENTION
Circuits that are designed to be manufactured on dies of a silicon wafer are later processed by an insertion tool that inserts scan cells to be used in testing the performance of the circuit for fault analysis and detecting design or manufacturing defects. The scan cells are generally flip-flops or other similar logical elements existing between stages of combinational logic within the circuit modified to permit serial access. The scan cells allow testing of the circuit beyond merely applying inputs and obtaining outputs on the external pins of the chip. Instead, scan cells allow an appropriately configured tester to apply and observe logical patterns at internal circuit nodes or nets. In such a manner, a tester typically designates specific voltage or logical values within the circuit at intermediate points throughout the combinational logic flow. Allowing the introduction of such voltages at intermediate nets of the circuit allows a more complete and effective means of testing the circuit for design and manufacturing defects.
Test quality of circuits is generally measured using the stuck-at fault testing model. In a stuck-at fault testing model, various nets of the circuit are tested by applying patterns of values inserted via the scan cells to determine if appropriate voltage values are obtained at the nets. For example, if a series of values is applied to the scan cells within the circuit such that the voltage value at a particular net should be at a high voltage level, but the voltage level at the particular net remains at a low voltage level, a stuck-at fault is detected. Given information about a particular circuit's design, manufacture, and logic flow, a stuck-at fault dictionary can be generated containing entries for each particular net that shows how the circuit would respond in the presence of those stuck-at-faults. Such flaws may include, but are not limited to, pin faults, element failures, metallization failures, improper metal oxidation, or incorrect ion implantation.
However, not all problems in a circuit can be detected using stuck-at fault testing models. Stuck-at fault models may not present a design or manufacturing team with sufficient information to easily determine the causes of particular faults that are detected in a circuit. Other faults, known as bridging faults, include faults that are the result of defects or failures involving more than one particular net. For example, two metal leads within a particular circuit layer or in adjacent circuit layers may be shorted, causing a fault that may not be easily detected or diagnosed using a stuck-at fault model of testing.
Despite the need for specific testing of bridging faults, commercial test pattern generators available today typically only follow stuck-at fault testing models. The high cost and amount of processing time required for a commercial test pattern generator to test all of the possible bridge faults within a particular circuit make such testing prohibitive. Even existing attempts to use stuck-at fault testing to predict possible bridging faults require far too much processing time to analyze possible bridging fault candidates as to make such prediction commercially infeasible. For example, attempts to use the physical layout and other physical circuit data prior to testing is computationally difficult. Another difficulty in diagnosing bridging faults lies in the fact that current testing using commercial tools provides too lengthy a diagnostic list making it very difficult to diagnose faults without some further means of automated analysis.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen for a system and method for pruning a bridging diagnostic list. The present invention provides a system and method for pruning a bridging diagnostic list that addresses the shortcomings of prior systems and methods for detecting and diagnosing bridging faults.
In one embodiment of the present invention, a system for generating a pruned diagnostic list of potential bridging faults in a circuit comprises a pattern generator operable to generate test patterns for testing a circuit and a tester in communication with the pattern generator that is operable to apply the test patterns to the circuit and generate a plurality of resultant vectors. The system also includes a stuck-at fault dictionary including a list of a plurality of nets of the circuit, each net having at least one resultant vector that indicates a potential stuck-at fault at the net. The system further includes a test analysis tool in communication with the pattern generator and the tester, the test analysis tool operable to create an initial logical diagnostic list of tested nets of the circuit associated with the potential stuck-at faults indicated in the stuck-at fault dictionary, the initial logical diagnostic list created in response to the generated plurality of resultant vectors. The system also includes a diagnostic tool in communication with the test analysis tool and the tester, the diagnostic tool operable to create a final logical diagnostic list using the resultant vectors, stuck-at fault dictionary, and the initial logical diagnostic list, the final logical diagnostic list having a plurality of potential bridging faults ranked in order of logical probability. The system additionally includes a physical database including physical data associated with each of a plurality of nets of the circuit and a pruning module in communication with the diagnostic tool and the physical database. The pruning module is operable to modify the final logical diagnostic list in response to the physical data to create the pruned diagnostic list, the pruned diagnostic list including a list of entries associated with a plurality of the most probable potential bridging faults.
In another embodiment of the invention, a system for generating a pruned diagnostic list of potential bridging faults in a circuit comprises a final logical diagnostic list of potential bridging faults, each potential bridging fault associated with at least two nets of the circuit, the final logical diagnostic list created in response to resultant vectors generated by a tester during testing for potential stuck-at-faults at a plurality of nets of the circuit. The system further comprising a physical database including physical data associated with each of the plurality of nets of the circuit and a pruning module in communication with the physical database. The pruning module is operable to apply adjacency criteria to the at least two nets of the circuit associated with each of the potential bridging faults in the final logical diagnostic list and to create the pruned diagnostic list of potential bridging faults.
In yet another embodiment of the invention, a method for generating a pruned diagnostic list of potential bridging faults in a circuit includes creating a final logical diagnostic list of potential bridging faults in response to testing the circuit for stuck-at-faults at a plurality of nets of the circuit, each potential bridging fault being associated with at least two tested nets of the circuit. The method further includes receiving physical data associated with each of the tested nets of the circuit and applying adjacency criteria to the physical data associated with the at least two tested nets that are associated with each of the listed potential bridging faults. The method also includes generating the pruned diagnostic list of potential bridging faults in response to applying the adjacency criteria.
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B. Chess, D. B. Lavo, F. J. Ferguson, and T. Larrabee, “Diagnosis of Realistic Bridging Faults with Single Stuckat Information,”IEEE—Proceedings of I
Balachandran Hari
Butler Ken
Saxena Jayashree
Brady W. James
De'cady Albert
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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