4. Error detection/correction and fault detection/recovery
  5. Pulse or data error handling
  6. Digital logic testing

Michael Ricchetti

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Method and apparatus for embedded built-in self-test (BIST)...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Method and apparatus for embedded built-in self-test (BIST)...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Method and apparatus for optimized parallel testing and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Method and apparatus for optimized parallel testing and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Method and apparatus for providing optimized access to...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate

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Profile ID: LFUS-PAI-P-2407473

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