System and method for controlling the access and refresh of...

Details System and method for controlling the access and refresh of... System and method for controlling the access and refresh of...

2007-03-06

2007-03-06

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S194000, C365S049130

Reexamination Certificate

active

11193805

ABSTRACT:
The present invention provides a memory and memory control system wherein, except for one case noted below, the main memory gives priority to read or write operations over refresh operations. On the other hand, the cache memory give priority to the refresh operations over read or write operations. The exceptional case is when a memory read signal is received when the cache refresh is enabled and the data in the cache memory is valid. In this exceptional case, the refresh of the cache memory is delayed. During certain read operations the data in the particular memory block is also written to the cache and no write back from the cache is performed. This reduces the number of write back operations and it eliminates a delay due to the refresh operation.

REFERENCES:
patent: 6370073 (2002-04-01), Leung
patent: 6615309 (2003-09-01), Tsuchida et al.
patent: 6697909 (2004-02-01), Wang et al.
patent: 6757784 (2004-06-01), Lu et al.
patent: 6930944 (2005-08-01), Hush
patent: 2003/0033492 (2003-02-01), Akiyama et al.
patent: 2002-0057307 (2002-07-01), None
English language abstract of Korean Publication No. 2002-0057307.

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