Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2006-07-18
2006-07-18
Nguyen, Tuan T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S189030, C365S190000
Reexamination Certificate
active
07079427
ABSTRACT:
A memory device is provided, which includes a first device, a second device, and a memory cell. The first device is electrically connected to a first plurality of wires. The first device is adapted to generate a small swing signal in the first plurality of wires. The second device is electrically connected to the first device by the first plurality of wires. The memory cell is electrically connected to the second device by a second plurality of wires. The second device is adapted to sense a small swing signal in the first plurality of wires, and to generate a full swing signal on the second set of wires in response to the small swing signal. The memory cell stores the full swing signal.
REFERENCES:
patent: 4764900 (1988-08-01), Bader et al.
patent: 4875169 (1989-10-01), Synovec et al.
patent: 4920517 (1990-04-01), Yamauchi et al.
patent: 5596521 (1997-01-01), Tanaka et al.
patent: 5781466 (1998-07-01), Tanaka et al.
patent: 5818261 (1998-10-01), Perner
patent: 6172920 (2001-01-01), Dhong et al.
patent: 6442089 (2002-08-01), Fletcher et al.
patent: 6458644 (2002-10-01), Hardee
patent: 6552944 (2003-04-01), Fifield et al.
patent: 6643160 (2003-11-01), Hardee
patent: 6930941 (2005-08-01), Nakase
patent: 2003/0002349 (2003-01-01), Pilo et al.
Osaka, K-I, et al., “A 2ns Access, 285MHz, Two-Port Cache Macro Using Double Global Bit-Line Pairs,” IEEE International Solid-State Circuits Conference (1997) pp. 402-403, 494.
Zhao, C., et al., “An 18-Mb, 12.3-GB/s CMOS Pipeline-Burst Cache SRAM with 1.54 Gb/s/pin,” IEEE Journal of Solid-State Circuits, vol. 34, No. 11 (Nov. 1999) pp. 1564-1570.
Nguyen Dang
Nguyen Tuan T.
Slater & Matsil L.L.P.
Taiwan Semiconductor Manufacturing Company , Ltd.
LandOfFree
System and method for a high-speed access architecture for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for a high-speed access architecture for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for a high-speed access architecture for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3603973