Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1997-08-11
1999-09-28
Dinh, Son T.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
36518912, 365233, G11C 700
Patent
active
059599006
ABSTRACT:
In a synchronous DRAM including a register having an input gate and an output gate, for holding read-out data between the input gate and the output gate by opening the input gate, and for transferring or outputting the held data by opening the output gate. An input gate control circuit for controlling an open/close of the input gate is supplied with a output switch feedback signal in the form of a one-shot pulse generated by an output gate control circuit for controlling an open/close of the output gate, in synchronism with an output gate switch signal, so that only after the data held in the register has been outputted to an external of the register, the next data to be succeedingly transferred from the read/write bus to the register is actually latched in the register.
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patent: 5530670 (1996-06-01), Matsumoto
patent: 5566124 (1996-10-01), Fudeyasu et al.
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Dinh Son T.
NEC Corporation
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