Synchronous semiconductor memory device having an auto-precharge

Static information storage and retrieval – Read/write circuit – Precharge

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Details

365191, 365194, G11C 800

Patent

active

055555268

ABSTRACT:
A semiconductor memory device according to the present invention having a plurality of memory banks, a row address strobe signal buffer, a column address strobe signal buffer and a column address generator and performing a data access operation in response to the burst length and latency information related to a system clock having a predetermined frequency, comprises a device for generating a signal which automatically precharges one memory bank of the memory banks in response to the row address strobe signal and the signal having the burst length and latency information after an address operation for the memory bank is completed.

REFERENCES:
patent: 4581722 (1986-04-01), Takemae
patent: 4636989 (1987-01-01), Ikuzaki
patent: 4907199 (1990-03-01), Dosaka
patent: 5430680 (1995-07-01), Parris

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