Synchronous memory devices having dual port capability for graph

Details Synchronous memory devices having dual port capability for graph Synchronous memory devices having dual port capability for graph

1999-08-27

2000-08-22

Nelms, David

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365233, G11C 700

Patent

active

061082449

ABSTRACT:
Graphics memory devices include an output register having an input electrically coupled to an output signal line (DO) and first and second data output buffers responsive to first and second clock signals (CLK1, CLK2), respectively. The first data output buffer has an input electrically coupled to the output signal line (DO) and the second data output buffer has an input electrically coupled to an output of the output register. These memory devices also include at least one memory cell array and a read data driver that has an input electrically coupled to the memory cell array by an input/output signal line (I/O) and an output electrically coupled to the output signal line (DO). To provide improved performance for graphics processing applications, a clock signal generator is provided that generates the first and second clock signals at different frequencies and/or different phases relative to each other. The second clock signal is preferably generated at a higher frequency than the first clock signal so that data (e.g., screen refresh data) provided by the read data driver to the output register can be serially transmitted from the second data output buffer at a high data rate. This data can also be transmitted in parallel with data being transmitted from the first data output buffer. In particular, the first data output buffer generates data at its output (first port) in response to a rising or falling edge of the first clock signal, but the second data output buffer generates data at its output (second port) in response to rising and falling edges of the second clock signal. Thus, even if the first and second clock signals have the same frequency, the rate of data being transmitted by the second data output buffer can be higher than the rate of data being transmitted by the first data output buffer.

REFERENCES:
patent: 4344131 (1982-08-01), Girard
patent: 4485414 (1984-11-01), Baker
patent: 5307324 (1994-04-01), Nishimoto

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