Surface mount die: wafer level chip-scale package and process fo

Details Surface mount die: wafer level chip-scale package and process fo Surface mount die: wafer level chip-scale package and process fo

1998-02-26

2000-06-13

Whitehead, Jr., Carl

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

257738, 257778, H01L 2348

Patent

active

060752904

ABSTRACT:
Disclosed is an IC package. The IC package includes a die having a plurality of conductive pads. A passivation layer is formed over the conductive pads such that the passivation layer has a plurality of passivation vias. Each passivation via is positioned over an associated one of the conductive pads. A resilient protective layer is formed over the passivation layer. The resilient protective layer has a plurality of resilient vias, wherein each resilient via is associated with an associated passivation via. A plurality of under bump pads are in electrical contact with the conductive pads, and each under bump pad is associated with one of the resilient vias. A plurality of contact bumps are formed over the plurality of under bump pads such that each one of the contact bumps is electrically coupled with a selected one of the under bump pads and such that each contact bump is electrically coupled with a selected one of the conductive pads. The resilient protective layer is arranged to absorb stresses introduced at the contact bumps when the IC package is attached to an external substrate; the contact bumps are formed from a material that facilitates absorption of stresses by the resilient protective layer, and the resilient protective layer is further arranged to protect the die. In one preferred embodiment, each under bump pad includes a lip that extends over a portion of the resilient layer. In another preferred embodiment, the contact bumps are formed from a eutectic tin-lead alloy. In another embodiment, a circuit board is disclosed. The circuit board includes a substrate having a plurality of board contacts and the IC package as recited above. In this embodiment, the IC package is attached to the substrate such that each of the contact bumps is coupled with an associated one of the board contacts. In a preferred embodiment, the resilient protective layer of the IC package absorbs stresses introduced at the contact bumps such that an underfill layer is not required between the IC package and the substrate.

REFERENCES:
patent: 5834844 (1998-11-01), Akagawa et al.
C4 Product Design Manual, Chapter 1--Technology Overview, Issue: A, pp. 1-5 through 1-8.

Affiliated with

Also associated with

Rating

Surface mount die: wafer level chip-scale package and process fo does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Surface mount die: wafer level chip-scale package and process fo, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Surface mount die: wafer level chip-scale package and process fo will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2070725