Surface mount chip package

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds

Reexamination Certificate

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Details

C257S778000, C257S797000

Reexamination Certificate

active

10736618

ABSTRACT:
A surface mount chip package comprises a package housing made of a prescribed resin, which is formed to cover a semiconductor chip while avoiding a plurality of conductors extending from the semiconductor chip. A plurality of solder balls are arranged in the package housing in correspondence with a main surface of the semiconductor chip having an integrated circuit and are interconnected with the conductors respectively. An index serving as a marking member is arranged together with the solder balls so as to bring a directivity realized by the shape thereof when viewed in the thickness direction of the semiconductor chip. This allows a user to easily recognize the inclination and position of the package housing without using the solder balls in view of the index, thus establishing a prescribed positioning for an electrical test such as a probing test.

REFERENCES:
patent: 6495916 (2002-12-01), Ohuchi et al.
patent: 6787892 (2004-09-01), Furuya et al.
patent: 3-142848 (1991-06-01), None
patent: 04-323836 (1992-11-01), None
patent: 2001-144197 (2001-05-01), None
patent: 2002-176265 (2002-06-01), None
patent: 399779 (2000-07-01), None
Taiwanese Office Action dated Jun. 7, 2005 (w/English translation of relevant portions).

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