Surface modified interconnects

Details Surface modified interconnects Surface modified interconnects

2001-11-08

2003-05-20

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06566211

ABSTRACT:

BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to interconnect structures and fabrication methods.
BACKGROUND: ALUMINUM METALLIZATION
Aluminum-based interconnects have been widely used for more than twenty years. With the rapid scaling of device dimensions, fine and highly reliable aluminum-based interconnects are required. However, fine interconnects are susceptible to failures due to higher mechanical stress and electron wind stress (electromigration). Electromigration is a phenomenon where fine metal lines will gradually develop gaps in response to current passing through them. Stress-induced metal ruptures are caused by void formation which occurs at specific grain boundaries where the <111> planes of adjoining grains come into contact. Moreover, stress-induced voiding affects electromigration failure because of the flux divergence around the voids.
The addition of copper greatly improves the electromigration (EM) lifetime of aluminum interconnects. Longer EM lifetimes improve the product reliability. Thus, typical aluminum alloys may use silicon (typically one-half percent to one percent atomic) or copper (typically one-half percent to one percent atomic) or both as alloying agents. Efforts have been made to find other satisfactory aluminum alloy compositions; see e.g. Kikuta and Kikkawa, “Electromigration characteristics for Al—Ge—Cu,” 143 J. Electrochem. Soc. 1088 (1996), which is hereby incorporated by reference.
In addition, as metal spacing becomes tighter and current density in metal leads increases, side hillocks become an important issue. This may be especially true for structures which include soft low density dielectrics, such as polymers and xerogels, between the interconnects. Furthermore, there are many dielectric materials which can not reliably be applied directly to a wafer when aluminum, exposed during a metal etch, is not first covered with some other material. Additionally, residues left on the sidewalls of interconnects after metal etch may contain chlorine or other elements which can promote corrosion. The addition of copper to the aluminum interconnect further increases the susceptibility of the interconnect to corrosion. Also, the solvents in which some dielectric materials are delivered may promote corrosion. A discussion of the corrosion susceptibility of aluminum alloy films is discussed in the following article: Lawrence et al., “Corrosion Susceptibility of Al—Cu and Al—Cu—Si Films,” IEEE/IRPS, p.102-06 (1991), which is hereby incorporated by reference.
One conventional approach to the problems of metal corrosion and dielectric adhesion is to deposit a barrier layer immediately following metal etch and clean-up. This layer serves to protect the metal lines by acting as a barrier to moisture (which could react with the residue on the side of the line) and other chemicals, and by acting as a “buffer” or “adhesion” layer to subsequently deposited dielectrics. However, the barrier layer is usually a dielectric material, such as silicon oxide or PETEOS, which may not necessarily be conformally deposited. Additionally, most dielectric materials neither possess sufficient diffusion barrier properties nor provide sufficient adhesion for the subsequent dielectric deposition.
BACKGROUND: REACTIVE REFRACTORY METALS
Reactive refractory metals (such as titanium) are advantageous for use in via hole applications due to their ability to getter impurities. Furthermore, when a reactive refractory metal is deposited on the top or bottom of an interconnect, the refractory metal can react with the metal interconnect (e.g. aluminum alloy) to form an intermetallic, which advantageously enhances the electromigration robustness of the interconnect.
For example, as described in U.S. Pat. No. 5,360,995 to Graas, which is hereby incorporated by reference, an intermetallic buffer layer on top of the interconnect can be formed by depositing a thin metal, such as titanium, between the interconnect material (e.g. aluminum) and the anti-reflective coating. Heating the metal causes it to react with the aluminum and form an intermetallic coating. The intermetallic coating protects the underlying interconnect material during via etching by providing a buffer that the etch can stop in.
BACKGROUND: VIA MISALIGNMENT
As device dimensions shrink, the overlap between the edges of vias and the edges of interconnects decreases. If a via is patterned such that it is not directly over an interconnect, the area of the via not overlying the interconnect may be too small (e.g. 50-100 nm) to be sputter-filled with a barrier layer prior to filling the vias with an additional metal (e.g. tungsten). This unadvantageously leaves at least part of the interconnect sidewall exposed during the subsequent tungsten deposition, which can corrode the aluminum interconnect. Also, there may be materials between the interconnects, which if exposed during via etch, can cause problems during the filling of the vias, such as via poisoning. The occurrence of via misalignment increases in “zero-overlap” via/interconnect designs, in which the area of the interconnect equals the area of the via.
One conventional approach of ensuring a reliable contact will still be made in the event of an error in contact via placement is to form a thick buffer region
620
, which can be composed of a dielectric, conductive nitride, polysilicon, or metal, on the sidewalls of the interconnect
610
to serve as an etch stop in order to protect the underlying layer
600
, as shown in prior art FIG.
6
. The buffer regions serve to significantly increase the line to space ratio, as discussed in U.S. Pat. No. 5,321,211 to Haslam et al., which is hereby incorporated by reference.
Conductive Sidewall Interconnect Structures and Methods
The present application discloses an interconnect structure having thin conductive sidewalls for enhanced yield, performance and reliability. This conductive sidewall is generally a refractory metal, but may also be a nitride, such as TiN. The primary purpose of the conductive sidewalls is suppress the formation of hillocks and to improve the electromigration resistance. Secondary purposes include gettering sidewall impurities, residual polymers, and corrosive species by-products from the plasma etch and cleanup processes used to pattern interconnects. In a preferred embodiment, a refractory metal reacts with the conducting layer to form an intermetallic which further enhances the endurance of the metallization against stress-induced ruptures and via-induced electromigration. Unlike the Haslam patent, which uses a thick sidewall buffer layer as an etch stop, the present inventors have discovered that the use of a thin conductive sidewall layer and/or alloyed region increases the electrical/structural reliability of interconnect structures, without significantly increasing the line to space ratio. The disclosed structures and methods are particularly advantageous in “zero-overlap” designs, and aggressive pitch patterns where linewidth and corrosion control are critical, but are also advantageous in “Damascene” pattern definition applications.
Advantages of the disclosed methods and structures include:
increases back-end-of-line yield by saving misaligned vias;
reduces the occurrence of associated failure mechanisms (such as certain types of intra-level oxide breakdown mechanisms) by avoiding leakage paths due to etch residues left on interconnect sidewalls;
lowers the resistance and improves the reliability of “zero-overlap” vias;
requires only a blanket deposition/etch for a very thin metal film;
does not impact linewidth control;
better sidewall rupturing endurance (because the intermetallic puts the aluminum sidewall under compression);
improved corrosion resistance;
enhanced resistance to hillock formation;
enhanced resistance to stress-voiding formation; and
gettering of impurities from the sidewalls of the interconnects.


REFERENCES:
patent: 5321211 (1994-06-01), Haslam et al.
patent: 5360995 (1994-11-01), Graas
patent: 5565708 (1996-10-01), Ohsaki et al.
patent: 5700718

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