Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
2010-01-15
2011-12-27
Kindred, Alford (Department: 2181)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S022000
Reexamination Certificate
active
08086766
ABSTRACT:
A method and apparatus for distributed parallel messaging in a parallel computing system. A plurality of DMA engine units are configured in a multiprocessor system to operate in parallel, one DMA engine unit for transferring a current packet received at a network reception queue to a memory location in a memory FIFO (rmFIFO) region of a memory. A control unit implements logic to determine whether any prior received packet destined for that rmFIFO is still in a process of being stored in the associated memory by another DMA engine unit of the plurality, and prevent the one DMA engine unit from indicating completion of storing the current received packet in the reception memory FIFO (rmFIFO) until all prior received packets destined for that rmFIFO are completely stored by the other DMA engine units. Thus, there is provided non-locking support so that multiple packets destined for a single rmFIFO are transferred and stored in parallel to predetermined locations in a memory.
REFERENCES:
patent: 2004/0052258 (2004-03-01), Robertson
patent: 2004/0054857 (2004-03-01), Nowshadi
patent: 2006/0161694 (2006-07-01), Tomozaki et al.
patent: 2009/0006546 (2009-01-01), Blumrich et al.
patent: 2009/0006662 (2009-01-01), Chen et al.
patent: 2009/0006666 (2009-01-01), Chen et al.
Chen Dong
Heidelberger Philip
Salapura Valentina
Senger Robert M.
Steinmacher-Burow Burkhard
International Business Machines - Corporation
Kindred Alford
Martinez David
Morris, Esq. Daniel P.
Scully , Scott, Murphy & Presser, P.C.
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