4. Multiplex communications
  5. Data flow congestion prevention or control
  6. Flow control of data transmission through a network

Valentina Salapura

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Architectural support for thread level speculative execution

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate

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Dynamic reallocation of data stored in buffers based on...

Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate

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Insertion of coherence requests for debugging a multiprocessor

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate

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Low complexity speculative multithreading system based on...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate

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Low complexity speculative multithreading system based on...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate

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Profile ID: LFUS-PAI-P-2223539

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