Structured strained substrate for forming strained...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S419000, C438S405000, C257SE21546, C257SE21115

Reexamination Certificate

active

08030148

ABSTRACT:
In a strained SOI semiconductor layer, the stress relaxation which may typically occur during the patterning of trench isolation structures may be reduced by selecting an appropriate reduced target height of the active regions, thereby enabling the formation of transistor elements on the active region of reduced height, which may still include a significant amount of the initial strain component. The active regions of reduced height may be advantageously used for forming fully depleted field effect transistors.

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patent: 2008/0213962 (2008-09-01), Clifton
Lei et al., “Strain relaxation in patterned strained silicon directly on insulator structures,”Applied Physics Letters, 87:251926-1-3, 2005.
PCT Search Report from PCT/EP2009/006261 dated Mar. 4, 2010.
PCT Preliminary Report on Patentability from PCT/EP2009/006261 dated Nov. 10, 2010.

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