Semiconductor device including interconnects, vias...

Details Semiconductor device including interconnects, vias... Semiconductor device including interconnects, vias...

2009-05-08

2011-10-11

Brewster, William M. (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S775000

Reexamination Certificate

active

08035232

ABSTRACT:
An interlayer insulating film is formed on the upper surface of a semiconductor substrate, and lower-level interconnects are formed in the interlayer insulating film. A liner insulating film is formed on the upper surfaces of the interlayer insulating film and lower-level interconnects. An interlayer insulating film is formed on the upper surface of the liner insulating film. Upper-level interconnects are formed in the interlayer insulating film. The lower-level interconnects and the upper-level interconnects are connected with each other through vias. Parts of the liner insulating film formed in via-adjacent regions have a greater thickness than a part thereof formed outside the via-adjacent regions.

REFERENCES:
patent: 7391115 (2008-06-01), Usami et al.
patent: 2003/0116854 (2003-06-01), Ito et al.
patent: 2006/0163739 (2006-07-01), Komai et al.
patent: 2006/0202336 (2006-09-01), Kajita et al.
patent: 2006-135220 (2006-05-01), None
patent: 2006135220 (2006-05-01), None
patent: WO 00/19498 (2000-04-01), None
Japanese Notice of Reasons for Rejection, w/ English translation thereof, issued in Japanese Patent Application No. JP 2008-125135 dated Jul. 6, 2010.
Arnal, V., et al., “45 nm Node Multi Level Interconnects with Porous SiOCH Dielectric k=2.5”, 2006, pp. 213-215, IITC.

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