Structure for folded architecture pillar memory cell

Details Structure for folded architecture pillar memory cell Structure for folded architecture pillar memory cell

2000-06-28

2002-08-27

Faumy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S270000, C438S294000, C257S330000, C257S302000

Reexamination Certificate

active

06440801

ABSTRACT:

RELATED APPLICATIONS
The following patent applications are assigned to the assignee hereof and contain subject matter related to the subject matter of the present patent applications:
1. U.S. patent application Ser. No. 08/787,419, entitled “4F-Square Memory Cell Having Vertical Floating-Gate Transistors with Self-Aligned Shallow Trench Isolation”, filed on even date herewith for Jeffrey J. WELSER, Hussein I. HANAFI, Stuart M. BURNS, and Waldemar W. KOCON;
2. U.S. patent application Ser. No. 08/792,955, entitled “Self-Aligned Diffused Source Vertical Transistors with stack Capacitors in a 4F-Square Memory Cell Array”, filed on even date herewith for Jeffrey J. WELSER, Hussein I. HANAFI, Stuart M. BURNS, Waldemar W. KOCON, and Howard L. KALTER; and
3. U.S. patent application Ser. No. 08/792,952, entitled “Self-Aligned Diffused Source Vertical Transistors with Deep Trench Capacitors in a 4F-Square Memory Cell Array”, filed on even date herewith for Jeffrey J. WELSER, Hussein I. HANAFI, Stuart M. BURNS, and Howard L. KALTER.
4. U.S. patent application Ser. No. 08/787,418, entitled “2F-Square Memory Cell for Gigabit Memory Applications,” filed on an even date herewith for Jeffrey J. WELSER, Hussein I. HANAFI, and Stuart M. BURNS.
The contents of the above-listed patent applications are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention is directed to densely packed vertical transistors in a 4F-square memory cell, and methods for making thereof, and more particularly, to memory cells having self aligned source with stack capacitors formed over vertical transistors.
2. Discussion of the Prior Art
There is much interest to scale down densely packed semiconductor devices on an integrated circuit (IC) chip to reduce size and power consumption of the chip, and allow faster operation. In order to achieve the high packing density necessary for Gbit memory application, it is crucial to shrink the size of an individual memory cell as much as possible.
FIG. 1
shows a top view of a conventional array
10
of conventional erasable programmable read only memory (EPROM) devices
15
, using vertical transistors, such as metal oxide silicon field effect transistors (MOSFETs) with a floating gate layer. The conventional array
10
is described in the following two references. H. Pein and J. D. Plummer, “A 3-D sidewall flash EPROM call and memory array”, Electron Device Letters, Vol. 14 (8) 1993 pp. 415-417. H. Pein and J. D. Plummer, “Performance of the 3-D Pencil Flash EPROM Cell and Memory Array”, IEEE Translations on Election Devices, Vol. 42, No. 11, 1995, pp. 1982-1991.
The conventional array
10
has rows of wordlines
20
and columns of bitlines
25
. The size of a cell
27
of the array
10
is 2F by 2F&Dgr;, leading to a cell area of 4F
2
+2F&Dgr;. F is the minimum line width of the feature size that can be patterned with lithography. 2F is the cell size along the wordline
20
, and 2F+&Dgr; is the cell size along the bitline
25
. Typically, &Dgr; is approximately 0.2F, resulting in a cell area of approximately 4F
2
+0.4F area achievable using conventional lithography. The additional length A is necessary to separate adjacent wordlines
20
.
FIG. 2
shows a partial perspective view of the array
10
of
FIG. 1
, and
FIG. 3
shows a cross sectional view of the vertical MOSFET
15
along a bitline
25
.
As shown in
FIG. 3
, the MOSFET
15
has an n source
30
formed on a P-doped silicon substrate
35
. The source
30
is formed after etching the substrate
35
to form a vertical pillar
40
, referred to as the body of the MOSFET
15
. The pillar
40
acts as the transistor channel and has dimensions of F by F, as shown in
FIGS. 1 and 3
.
As a result of forming the source
30
after forming the pillars
40
, the source
30
is formed around edges of the pillar
40
and is absent from a region
45
located below the pillar
40
. Thus, the source
30
does not entirely occupy the footprint of the pillar
40
. As shown in
FIG. 2
, all the MOSFETs
15
of the array
10
have a common source
30
, including MOSFETs of different bitlines
25
and different wordlines
20
. As shown in
FIGS. 2-3
, the top of each pillar
40
is doped with N-type material to form n drains
50
of the vertical transistors
15
.
A tunnel oxide
60
is formed around the pillar
40
and an oxide spacer
65
is formed on the source
30
. Next, a polysilicon floating gate
70
, gate oxide
75
and polysilicon gate
20
are formed around the tunnel oxide
60
. Note, control gates
20
of individual transistors along the wordline
20
are inter-connected to form the wordline
20
.
Because the polysilicon control gate
20
grows uniformly around each vertical MOSFET
15
, the spacing between MOSFETs
15
of adjacent rows is slightly larger than the feature size F, e.g., F+&Dgr;, where &Dgr; is approximately 0.2F. This separates adjacent wordlines
20
by amount &Dgr;, when polysilicon is grown up to a distance of 0.5F. This 0.5F thick polysilicon layer covers the top and sidewalls of the pillars
40
, as well as the oxide spacer
65
located on the substrate
35
at the base of the pillars
40
.
The 0.5F thick grown polysilicon regions at pillar sidewalls separated by distance F, along each wordline
20
, merge with each other. This forms the wordlines
20
around a row of pillars that are separated by F. However, the 0.5F thick formed polysilicon regions at pillar sidewalls separated by distance F+&Dgr;, the oxide spacer
65
is covered with the 0.5F thick polysilicon.
To separate adjacent wordlines
20
, a reactive ion etch (RIE) is performed that removes polysilicon for a thickness of 0.5F. The RIE exposes the top of the pillars
40
, as well as the oxide spacer
65
at the base of the pillars that are separated by F+&Dgr;. The exposed distance of the oxide spacer
65
is &Dgr;. Thus, the &Dgr; separation between adjacent wordlines
20
ensures that control gates
20
of adjacent wordlines are not shorted along the direction of the bitlines
25
.
As shown in
FIGS. 1 and 2
, a first level metal forms bitlines
25
which are orthogonal to the wordlines
20
. The first level metal connects drains
50
of MOSFETs
15
along a common bitline
25
.
The area of the cell
27
of
FIG. 2
, is small because the substrate
35
is used as a common source
30
for all the MOSFETs
15
of the array
10
.
FIG. 4
shows a three dimensional view of another conventional array
90
, which is similar to the conventional array
10
of
FIG. 2
, except for having round pillars
95
instead of square pillars
40
(FIG.
2
). As in the array
10
of
FIG. 2
, the array
90
of
FIG. 4
has a common source
30
.
The memory function of each cell
27
is achieved by charging or discharging the floating gate region
70
. This causes a measurable shift in the threshold voltage of the vertical MOSFET.
In the conventional EPROM cell
27
, the tunnel oxide between the floating gate
70
and the transistor channel or pillar
40
is fairly thick, having a thickness of at least 150Å. Therefore charging of the floating gate
70
must be achieved by flowing a large drain current. This generates hot electrons which can tunnel through the tunnel oxide
60
, often referred to as hot-electron injection or channel hot electron tunneling. However, channel hot electron tunneling is not suitable for DRAM or “Flash” memory application, because channel hot electron tunneling requires high power. This is particularly a problem in the high density arrays necessary for Gbit memories. In addition, tunnel oxide degradation caused by hot electron tunneling is not tolerable for application that require frequent read/write operations.
If the tunnel oxide
60
is made thinner, e.g., ≦3 nm, direct tunneling between the channel
40
and floating gate
70
is possible. In contrast to hot electron tunneling, direct tunneling is faster resulting in faster write and erase times, requires much lower power, and minimizes tunnel oxide degradation.
However, because the sources
27
of all

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