Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2002-12-12
2004-12-14
Clark, S. V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C438S629000, C438S639000
Reexamination Certificate
active
06831363
ABSTRACT:
BACKGROUND
The present invention relates generally to semiconductor device manufacturing and, more particularly, to a structure and method for reducing thermo-mechanical stress in stacked vias.
In the fabrication of integrated circuit devices, it is often desirable to isolate individual components of the integrated circuits from one another with insulative materials. Such insulative materials may include, for example, silicon dioxide, silicon nitride and silicon carbide. While these materials may have acceptable insulating properties in many applications, they also have relatively high dielectric constants, which can lead to capacitive coupling between proximate conductive elements. This is particularly disadvantageous, given the ever-decreasing distances between conductive circuit elements, and the use of multi-layered structures. An unnecessary capacitive coupling between adjacent wires increases the RC time delay of a signal propagated therethrough, resulting in decreased device performance. Thus, for specific applications, insulating materials having relatively low dielectric constants (e.g., &kgr;<3) are desired.
Certain organic polymers are known in the semiconductor manufacturing industry for their “low-k” dielectric properties, which polymers are often used for intermetallic insulation in damascene structures. These polymers are generally classified as aromatic thermosets, polyarylene ethers and crosslinked polyphenylene polymers. Examples of such polymers include SiLK® (manufactured by The Dow Chemical Company), FLARE® and GX3® (both manufactured by the Honeywell corporation). SiLK®, for instance, is typically applied to semiconductor wafers by spin-on coating in a wafer track, similar to the process used in the application of photolithography resist.
However, the integration of an all low-k dielectric like SiLK® in semiconductor manufacturing has presented several challenges such as, for example, the effects of thermal expansion differences between the low-k dielectric material and the interconnect materials (e.g., copper, oxide). In particular, the coefficient of thermal expansion (CTE) of SILK® is about 133 ppm up to 400-440° C. (SiLK® is cured between 400-450° C. during integration), whereas the CTE of copper and oxide is about 17 ppm and 4 ppm, respectively. As a result of this relatively large CTE differential, there are often stacked via failures (e.g., sheared vias) after about 1000 thermal cycles. In order to address this structural problem, prior approaches have replaced an all-SiLK® dielectric with a hybrid build of SiLK® and oxide in which the oxide is used entirely within the via level. One tradeoff, however, in replacing SiLK® with oxide at the via level is the higher RC delay due to the higher dielectric constant of the oxide. In addition, there is also a higher cost associated with single damascene hybrid build.
Accordingly, it is desirable to be able to take advantage of the low-k properties of dielectric materials such as SiLK®, while still maintaining structural integrity of the back end of line (BEOL) interconnects.
SUMMARY
The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by an interconnect structure for a semiconductor device including an organic, low dielectric constant (low-k) dielectric layer formed over a lower metallization level. A via formed is within the low-k dielectric layer, the via connecting a lower metallization line formed in the lower metallization level with an upper metallization line formed in an upper metallization level. The via is surrounded by a structural collar selected from a material having a coefficient of thermal expansion (CTE) so as to protect the via from shearing forces following a thermal expansion of the low-k dielectric layer.
In another aspect, a method for reducing thermo-mechanical stress in a semiconductor device interconnect structure includes forming an organic, low dielectric constant (low-k) dielectric layer formed over a lower metallization level. An opening is defined in the low-k dielectric layer and over a lower metallization line formed in said lower metallization level. The opening formed in the low-k dielectric layer is filled with a structural material having a coefficient of thermal expansion (CTE) sufficient to protect a via from shearing forces following a thermal expansion of the low-k dielectric layer. Then, a via opening is defined in the structural material and the via opening is thereafter filled with a conductive via material, wherein remaining portions of the structural material form a protective collar surrounding the via material.
In yet another aspect, a method for forming an interconnect structure for a semiconductor device includes forming an organic, low dielectric constant (low-k) dielectric layer over a lower metallization level, the low-k dielectric layer being formed at a sufficient thickness to define a via level over the lower metallization level and an upper metallization level over the via level. An opening is defined in the low-k dielectric layer and over a lower metallization line formed in the lower metallization level, the opening then being filled with a structural material having a coefficient of thermal expansion (CTE) sufficient to protect a via subsequently formed therein from shearing forces following a thermal expansion of the low-k dielectric layer. A via opening in then defined in the structural material, and an upper metallization line opening is defined over the via opening. The via opening and the upper metallization line opening are filled with a conductive material, thereby defining a via connecting the lower metallization to an upper metallization line, wherein remaining portions of the structural material form a protective collar surrounding the via.
REFERENCES:
patent: 6586334 (2003-07-01), Jiang
patent: 6599827 (2003-07-01), Ngo et al.
patent: 6605549 (2003-08-01), Leu et al.
patent: 6613664 (2003-09-01), Barth et al.
patent: 6620727 (2003-09-01), Brennan
Dalton Timothy J.
Das Sanjit K.
Engel Brett H.
Herbst Brian W.
Hichri Habib
Clark S. V.
International Business Machines - Corporation
Jaklitsch Lisa U.
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