Stress enhanced CMOS circuits and methods for their fabrication

Details Stress enhanced CMOS circuits and methods for their fabrication Stress enhanced CMOS circuits and methods for their fabrication

2006-09-18

2008-10-28

Smith, Matthew S. (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S369000, C257SE21632, C257SE27062

Reexamination Certificate

active

07442601

ABSTRACT:
A stress enhanced CMOS circuit and methods for its fabrication are provided. One fabrication method comprises the steps of forming an NMOS transistor and a PMOS transistor adjacent the NMOS transistor in a channel width direction, the PMOS transistor and the NMOS transistor separated by an isolation region. A compressive stress liner is deposited overlying the transistors and the isolation region and is etched to remove the compressive stress liner from the NMOS transistor and from a portion of the isolation region. A tensile stress liner is deposited overlying the transistors, the isolation region, and the compressive stress liner and is etched to remove a portion of the tensile stress liner overlying a portion of the compressive stress liner and to leave the tensile stress liner overlying the NMOS transistor, the isolation region, and a portion of the compressive stress liner.

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