Stratified underfill in an IC package

Details Stratified underfill in an IC package Stratified underfill in an IC package

2006-03-29

2010-02-02

Hoang, Quoc D (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

C438S108000, C257SE21503, C257SE21508

Reexamination Certificate

active

07656042

ABSTRACT:
A method includes joining an integrated circuit die having at least one low-k dielectric layer to a package substrate or printed circuit board using a plurality of solder bumps located between the die and the package substrate or printed circuit board. The low-k dielectric layer has a dielectric constant of about 3.0 or less. The solder bumps have a lead concentration of about 5% or less. A stratified underfill is formed between the die and the package substrate or printed circuit board.

REFERENCES:
patent: 6369451 (2002-04-01), Lin
patent: 6475828 (2002-11-01), Hoang
patent: 6740823 (2004-05-01), Shimizu
patent: 6773958 (2004-08-01), Wang
patent: 6774493 (2004-08-01), Capote et al.
patent: 6815831 (2004-11-01), Dias
patent: 7009307 (2006-03-01), Li
patent: 2004/0026782 (2004-02-01), Anzai
patent: 2005/0006766 (2005-01-01), Takubo et al.
patent: 2005/0087891 (2005-04-01), Rumer et al.

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