Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-03-27
2007-03-27
Chaudhari, Chandra (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S655000, C438S938000, C257SE21636
Reexamination Certificate
active
11026009
ABSTRACT:
A strained channel NMOS and PMOS device pair including fully silicided gate electrodes and method for forming the same, the method including providing a semiconductor substrate including NMOS and PMOS device regions including respective gate structures including polysilicon gate electrodes; forming recessed regions on either side of a channel region including at least one of the NMOS and PMOS device regions; backfilling portions of the recessed regions with a semiconducting silicon alloy to exert a strain on the channel region; forming offset spacers on either side of the gate structures; thinning the polysilicon gate electrodes to a silicidation thickness to allow full metal silicidation through the silicidation thickness; ion implanting the polysilicon gate electrodes to adjust a work function; and, forming a metal silicide through the silicidation thickness to form metal silicide gate electrodes.
REFERENCES:
patent: 6436754 (2002-08-01), Lee
patent: 6929992 (2005-08-01), Djomehri et al.
patent: 6939814 (2005-09-01), Chan et al.
Chan Bor-Wen
Chiu Yuan-Hung
Tao Han-Jan
Chaudhari Chandra
Taiwan Semiconductor Manufacturing Co. Ltd.
Tung & Associates
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