Static memory including data buffer and latch circuits

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

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365190, 365233, G11C 700

Patent

active

047945672

ABSTRACT:
A static memory circuit which can stably conduct a write operation with large margins is disclosed. The memory circuit comprises a plurality of static type memory cells, a first terminal for receiving input data to be written, a second terminal for receiving a control signal for changing an operation mode of the memory from a read operation mode to a write operation mode, a latch circuit for holding the input data during the write operation mode, and circuitry for applying the held data by the latch circuit to a selected memory cell.

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patent: 4300213 (1981-11-01), Tanimura et al.
patent: 4386419 (1983-05-01), Yamamoto
patent: 4397001 (1983-08-01), Takemae
patent: 4400801 (1983-08-01), Kible
patent: 4415994 (1983-11-01), Ive et al.
patent: 4507759 (1985-03-01), Yasui et al.
Ahlquist et al., "A 16K Dynamic RAM", IEEE International Solid State Circuits Conference, Digest of Technical Papers, Feb. 19, 1976, pp. 128-129.
Mostek Corp., "An In-Depth Look at the MK 4027", New Electronics, vol. 9, No. 12, pp. 58, 60, 64, Jun. 15, 1976.

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