Standard cell back bias architecture

Details Standard cell back bias architecture Standard cell back bias architecture

2006-10-03

2006-10-03

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S204000, C257SE27005, C257S108000

Reexamination Certificate

active

07115460

ABSTRACT:
An apparatus including, in one embodiment, a CMOS device cell including at least first and second CMOS transistors having first and second CMOS transistor doped regions in first and second doped wells, respectively, wherein each of the first and second CMOS transistor doped regions is configured to be biased with a corresponding one of a power supply potential and a ground potential. Such an embodiment also includes a tap cell having first and second tap cell doped regions in the first and second doped wells, respectively, wherein each of the first and second tap cell doped regions is configured to be biased with a different potential relative to the power supply and ground potential.

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Tadahiro Kuroda et al., “Substrate Noise Influence on Circuit Performance in Variable Threshold-Voltage Scheme”, 1996, pp. 309-312, ISLPED, Monterey, CA, USA, 0-7803-3571-8/96.
Kimiyoshi Usami et al., “Low-power Design Methodology and Application utilizing Dual Supply Voltages”, 6 pages.
Tadahira Kuroda et al., A High-Speed Low-Power 0.3um CMOS Gate Array with Variable Threshold Voltage (VT) Scheme, 1996, pp., 53-56, IEEE 1996 Customer Integrated Circuits Conference, 0-7803-3177-6.

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