Standard cell back bias architecture

Details Standard cell back bias architecture Standard cell back bias architecture

2008-01-01

2008-01-01

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S199000, C257SE21135, C257SE21632, C257SE23153

Reexamination Certificate

active

07314788

ABSTRACT:
An apparatus including, in one embodiment, a CMOS device cell including at least first and second CMOS transistors having first and second CMOS transistor doped regions in first and second doped wells, respectively, wherein each of the first and second CMOS transistor doped regions is configured to be biased with a corresponding one of a power supply potential and a ground potential. Such an embodiment also includes a tap cell having first and second tap cell doped regions in the first and second doped wells, respectively, wherein each of the first and second tap cell doped regions is configured to be biased with a different potential relative to the power supply and ground potential.

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Usami, Kimiyoshi, et al., “Low-Power Design Methodology and Applications Utilizing Dual Supply Voltages”, ACM Press, 200, pp. 123-128, date unknown.

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