Staggered in-situ deposition and etching of a dielectric...

Details Staggered in-situ deposition and etching of a dielectric... Staggered in-situ deposition and etching of a dielectric...

2002-09-04

2004-11-23

Chen, Bret (Department: 1762)

Coating processes

Direct application of electrical, magnetic, wave, or...

Plasma

C427S579000, C427S534000

Reexamination Certificate

active

06821577

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the fabrication of integrated circuits. More particularly, the present invention is directed toward a method and apparatus for increasing the deposition rate of a conformal dielectric layer, having excellent gap-filling characteristics, deposited over a stepped surface.
Semiconductor device geometries continue to decrease in size, providing more devices per unit area on a fabricated wafer. Currently, some devices are fabricated with feature dimensions as small as 0.18 &mgr;m. For example, spacing between conductive lines or traces on a patterned wafer may be separated by 0.18 &mgr;m leaving recesses or gaps of a comparable size. A nonconductive layer of dielectric material, such as silicon dioxide, is typically deposited over the features to fill the aforementioned gap and insulate the features from other features of the integrated circuit in adjacent layers or from adjacent features in the same layer.
One problem encountered, as the feature dimensions of the integrated circuits decrease, is that it becomes difficult to fill the gaps completely between adjacent conductive lines. This problem is referred to as the gap-fill problem and is described below in conjunction with
FIGS. 1 and 2
.
FIG. 1
shows a vertical cross-sectional view of a substrate
10
, such as a semiconductor wafer, having a layer of conductive features
12
, defining gaps, shown as
14
. The sidewalls
16
of the gap are formed by one edge of adjacent conductive features
12
. During deposition, dielectric material
18
accumulates on the surfaces
20
of the conductive features
12
, as well as the substrate
10
and forms overhangs
22
located at the corners
24
of the conductive features
12
. As deposition of the dielectric layer
16
continues, the overhangs
22
typically grow together faster than the gap
14
is filled until a dielectric layer
26
is formed, creating an interior void
28
, shown more clearly in FIG.
2
. In this fashion, the dielectric layer
26
prevents deposition into the interior void
28
. The interior void
28
may be problematic to device fabrication, operation, and reliability.
Many different techniques have been implemented to improve the gap-filling characteristics of dielectric layers, including deposition etch-back (dep-etch) techniques. One such dep-etch technique involves physical sputtering of the dielectric layer by ion bombardment to prevent the formation of voids during a deposition process. The effects of the physical sputtering dep-etch technique is shown in FIG.
3
. As shown in
FIG. 3
, ions
30
incident on the dielectric material transfer energy thereto by collision, allowing atoms
32
to overcome local binding forces and eject therefrom. During the dep-etch technique, dielectric material fills the gap
14
forming a surface
34
. The surface
34
lies in a plane that extends obliquely to the sidewalls
16
, commonly referred to as a facet. This dep-etch technique may be applied sequentially so that the dielectric layer
26
is deposited and then subsequently etched followed by deposition of additional dielectric material. Alternatively, the deposition process and the etch process may occur concurrently. Whether the deposition and etching are sequential or concurrent, the first order effects on the surface of the dielectric layer
26
's profile are the same.
Referring to
FIGS. 3 and 4
, after an extended dep-etch technique, the portion of the dielectric layer
26
positioned adjacent to the corners
24
, regardless of the spacing between the conductive features
12
, has a surface
34
that forms an oblique angle with respect to the plane in which the substrate
10
lies. Thereafter, planarization may be accomplished by an extended planarization etch technique where physical sputtering is balanced with the deposition so that very narrow features become completely planarized. Alternatively, a separate planarization process may be employed that is capable of smoothing or eliminating the remaining steps of the large features.
Typically, a plasmachemical vapor deposition (CVD) process is employed to deposit a dielectric layer using the dep-etch technique. For example, a plasma-enhanced chemical vapor deposition (PECVD) process, or a high-density plasma-chemical vapor deposition process, such as an electron cyclotron resonance chemical vapor deposition (ECR-CVD) process, may be employed. The plasma CVD processes typically allow deposition of high quality films at lower temperature and with faster deposition rates than are typically possible employing purely thermally activated CVD processes. However, the deposition rates available using conventional plasma CVD processes are still relatively low.
What is needed is a method and an apparatus for depositing a conformal dielectric layer over a stepped surface of a substrate at significantly faster rates than was previously possible in the prior art.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus for greatly increasing the deposition rate of a conformal dielectric layer employing a dep-etch technique. The invention does so by selectively increasing inert gas source concentration, in a process chamber, without a significant increase in chamber pressure.
The dielectric layer is deposited employing a high-density plasmachemical vapor deposition (HDP-CVD) system, such as an Applied Materials, Inc. Ultima HDP-CVD System. Typically, gaps having a high-aspect ratio of up to 2.5:1 may be present on a substrate upon which the dielectric layer is to be deposited, with the substrate being positioned in a process chamber of the HDP-CVD system. Deposition gases, such as a silicon source gas and an oxygen source gas are flowed across the surface of the substrate along with an inert gas. An RF source generator and an RF bias generator are each in electrical communication with the process chamber to form a plasma from the process and inert gases.
An important consideration during the dep-etch technique is that the deposition-to-etch ratio (dep-etch ratio) be maintained within a predetermined range so as to prevent over-etching and formation of interior voids. The present invention maintains the dep-etch ratio within a suitable range to prevent over-etch, while increasing the deposition rate of the dielectric layer to provide a 100% gap-fill of gaps having an aspect ratio up to 2.5:1. This is accomplished by rapidly increasing the etch rate of the dielectric layer, which allows increasing the deposition rate while maintaining a suitable dep-etch ratio. Specifically, it was discovered that the etch-rate of a dielectric layer is dependent not only upon the pressure of the process chamber, but also upon the concentration of the inert gas therein. The etch rate was found to be inversely proportional to the pressure in the process chamber and proportional to the concentration of inert gas present therein. By selectively terminating the flow of deposition gases in the process chamber, referred to as a staggered in-situ deposition technique, the pressure present therein may be decreased or maintained, while the inert gas concentration is substantially increased. In this fashion, the etch rate of the dielectric layer is substantially increased. The increased etch rate allows increasing the deposition rate using any deposition technique known to those skilled in the art. This decreases the time necessary to deposit the dielectric layer while maintaining a desired dep-etch ratio to provide the dielectric layer with superior gap-filling characteristics.
In a preferred embodiment, the silicon source gas includes silane gas, SiH
4
, and the oxygen source gas includes molecular oxygen gas, O
2
. The inert gas source is argon, Ar. The RF source generator operates at a source frequency of about 2 MHz and a source power level between about 12-16 W/cm
2
. The RF bias generator operates at a frequency of about 13.56 MHz and a power level between about 7-13 W/cm
2
. The process chamber pressure may be between about 2 and 10 millitorr, with 4-5 millitorr

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