Stacked double sidewall spacer oxide over nitride

Details Stacked double sidewall spacer oxide over nitride Stacked double sidewall spacer oxide over nitride

2001-02-07

2003-09-30

Chaudhuri, Olik (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S267000, C438S366000, C438S649000, C438S655000, C438S664000

Reexamination Certificate

active

06627504

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the fabrication of semiconductor devices, particularly to self-aligned silicide (salicide) technology, and the resulting semiconductor devices. The present invention is particularly applicable to ultra-large scale integrated circuit (ULSI) systems having features in the deep sub-micron regime.
BACKGROUND ART
As integrated circuit geometries continue to plunge into the deep sub-micron regime, it becomes increasingly more difficult to accurately form discrete devices on a semiconductor substrate exhibiting the requisite reliability. High performance microprocessor applications require rapid speed of semiconductor circuitry. The speed of semiconductor circuitry varies inversely with the resistance (R) and capacitance (C) of the interconnection system. The higher the value of the RxC product, the more limiting the circuit operating speed. Miniaturization requires long interconnects having small contacts and small cross-sections. Accordingly, continuing reduction in design rules into the deep sub-micron regime requires decreasing the R and C associated with interconnection paths. Thus, low resistivity interconnection paths are critical to fabricating dense, high performance devices.
A common approach to reduce the resistivity of the interconnect to less than that exhibited by polysilicon alone, e.g., less than about 15-300 ohm/sq, comprises forming a multilayer structure consisting of a low resistance material, e.g., a refractory metal silicide, on a doped polycrystalline silicon layer, typically referred to as a polycide. Advantageously, the polycide gate/interconnect structure preserves the known work function of polycrystalline silicon is directly on the gate oxide.
Various metal silicides have been employed in salicide technology, such as titanium, tungsten, and cobalt. Nickel, however, offers particular advantages vis-à-vis other metals in salicide technology. Nickel requires a lower thermal budget in that nickel silicide can be formed in a single heating step at a relatively low temperature of about 250° C. to about 600° C. with an attendant reduction in consumption of silicon in the substrate, thereby enabling the formation of ultra-shallow source/drain junctions.
In conventional salicide technology, a layer of the metal is deposited on the gate electrode and on the exposed surfaces of the source/drain regions, followed by heating to react the metal with underlying silicon to form the metal silicide. Unreacted metal is then removed from the dielectric sidewall spacers leaving metal silicide contacts on the upper surface of the gate electrode and on the source/drain regions. In implementing salicide technology, it was also found advantageous to employ silicon nitride sidewall spacers, since silicon nitride is highly conformal and enhances device performance, particularly for p-type transistors. However, although silicon nitride spacers are advantageous from such processing standpoints, it was found extremely difficult to effect nickel silicidation of the gate electrode and source/drain regions without undesirable nickel silicide bridging and, hence, short circuiting, therebetween along the surface of the silicon nitride sidewall spacers.
SUMMARY OF THE INVENTION
There is a need for a method of manufacturing a semiconductor device having silicide contacts and gate electrode and associated source/drain regions without bridging therebetween along insulative sidewalls spacers, notably silicon nitride sidewall spacers.
These and other needs are met by embodiments of the present invention which provide a method of forming silicide on a semiconductor electrode device comprising the steps of forming on substrate a polysilicon gate electrode with sidewalls. Silicon nitride spacers are formed on the sidewalls and cover only a lower portion of the sidewalls. This leaves an upper portion of the sidewalls exposed. Barrier spacers are formed on the silicon nitride spacers and cover the upper portion of the sidewalls. A barrier spacers comprise silicon migration blocking material. A metal layer is formed over the gate electrode, the silicon nitride spacers, and the barrier spacers. Heating is then performed to react the metal layer with the gate electrode formed silicide. The barrier spacers substantially prevent silicon migration from the gate electrode during this heating step.
By providing barrier spacers that comprise silicon migration blocking material, silicide is prevented from forming on these silicon nitride spacers due to interaction of the metal with silicon that may otherwise migrate at the top of the nitride spacer. The prevention of silicide on the nitride spacers ensures that bridging does not occur between the gate electrode and silicide formed on active regions of the semiconductor device.
The earlier stated needs are also met by another embodiment of the present invention which provides a semiconductor device comprising a gate electrode which has opposing side surfaces and an upper surface. The gate electrode is provided on an upper surface of the semiconductor substrate with a gate insulating layer therebetween. Recessed silicon nitride spacers are provided on the opposing side surfaces and cover only a lower portion of these opposing side surfaces. On top of the silicon nitride spacers and on the opposing side surfaces are barrier spacers. These barrier spacers cover only an upper portion of the opposing side surfaces. A layer of silicide is provided on the upper surface of the gate electrode and another layer of silicide is provided on the substrate surface adjacent each silicon nitride sidewall spacer.
The semiconductor device of the present invention has a layer of silicide on the upper surface of gate electrode with a layer of silicide on the substrate surface, but these silicide layers are not connected by bridging silicide due to the barrier spacers provided on top of the silicon nitride spacers. The barrier spacers prevent formation of bridging silicide on the silicon nitride spacers, which may be caused by the migration of silicon at the top of the silicon nitride spacers in prior arrangements.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5889331 (1999-03-01), Bai
patent: 5923986 (1999-07-01), Shen
patent: 6406987 (2002-06-01), Huang

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