Stacked chip package using photosensitive polymer and...

Details Stacked chip package using photosensitive polymer and... Stacked chip package using photosensitive polymer and...

2006-05-18

2008-12-02

Clark, Jasmine J (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S777000, C257SE25006, C257SE25013, C257SE25018, C257SE25021, C257SE25027, C257SE25029

Reexamination Certificate

active

07459774

ABSTRACT:
In a stacked chip configuration, and manufacturing methods thereof, the gap between a lower and an upper chip is filled completely using a relatively simple process that eliminates voids between the lower and upper chips and the cracking and delamination problems associated with such voids. The present invention is applicable to both chip-level bonding and wafer-level bonding approaches. A photosensitive polymer layer is applied to a first chip, or wafer, prior to stacking the chips or stacking the wafers. The photosensitive polymer layer is partially cured, so that the photosensitive polymer layer is made to be structurally stable, while retaining its adhesive properties. The second chip, or wafer, is stacked, aligned, and bonded to the first chip, or wafer, and the photosensitive polymer layer is then cured to fully bond the first and second chips, or wafers. In this manner, adhesion between chips/wafers is greatly improved, while providing complete gap fill. In addition, mechanical reliability is improved, alleviating the problems associated with cracking and delamination, and leading to an improvement in device yield and device reliability.

REFERENCES:
patent: 6429096 (2002-08-01), Yanagida
patent: 2003/0107119 (2003-06-01), Kim
patent: 2003/0127724 (2003-07-01), Senba
patent: 2004/0238927 (2004-12-01), Miyazawa
patent: 2002-050738 (2002-02-01), None
patent: 2004-288722 (2004-10-01), None
patent: 10-2002-0012061 (2002-02-01), None
patent: 10-2006-0010099 (2006-02-01), None

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