Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1998-07-01
2000-08-08
Bowers, Charles
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438656, 438643, 438627, 257751, H01L 2144
Patent
active
061001880
ABSTRACT:
A metal-poly stack gate structure and associated method for forming a conductive barrier layer between W and poly in the metal-gate stack gate structure. The process includes the steps of depositing doped silicon on a substrate; forming nitride on the deposited silicon; depositing a metal on the nitride to form a metal
itride/deposited silicon stack; and thermally treating the stack to transform the nitride into a conductive barrier layer between the metal and the deposited silicon. The thermal treatment transforms the nitride layer (SiN.sub.x or SiN.sub.x O.sub.y) into a conductive barrier (WSi.sub.x N.sub.y or WSi.sub.x N.sub.y O.sub.z) to form a W/barrier/poly stack gate structure. The barrier layer blocks reaction between W and Si, enhances sheet resistance, enhances adhesion between the W and the poly, and is stable at high temperatures.
REFERENCES:
patent: 4715937 (1987-12-01), Moslehi et al.
patent: 5780908 (1998-07-01), Sekiguchi et al.
patent: 5907188 (1999-05-01), Nakajima et al.
Hezel et al. ; "Silicon Oxynitride Films Prepared by Plasma Nitridation of Silicon and Their Application for Tunnel Metal-Insulator-Silicon Diodes"; J. Appl. Phys., vol. 56, No. 6, Sep. 1984.
1996 IEEE Transactions on Electron Devices, vol. 43, No. 11, Nov. 1996, "Low-Resistivity Poly-Metal Gate Electrode Durable for High-Temperature Processing," pp. 1864-1869 (Yasushi Akasaka; Shintaro Suehiro; Kazuaki Nakajima; Tetsuro Nakasugi; Kiyotaka Miyano; Kunihiro Kasai; Hisato Oyamatsu, Member, IEEE; Masaaki Kinugawa, Member, IEEE; Mariko Takayanagi; Kenichi Agawa; Fumitomo Matsuoka, Member, IEEE; Masakazu Kakumu, Member, IEEE; and Kyoichi Suguro).
IEEE Transactions on Electron Devices, vol. ED-31, No. 9, Sep. 1984, "A New Tungsten Gate Process for VLSI Applications," pp. 1174-1179 (Seichi Iwata, Naoki Yamamoto, Nobuyoshi Kobayashi, Tomoyuki Terada, and Tatsumi Mizutani).
"A Novel Tungsten Gate Technology for VLSI Applications," pp. 94-95 (Nobuyoshi Kobayashi, Seichi Iwata, Naoki Yamamoto and Tomoyuki Terada).
1987 Materials Research Society "Highly Reliable Tungsten Gate Technology," pp. 159-167 (N. Kobayashi, S. Iwata, N. Yamamoto and N. Hara).
Anderson Dick N.
Carter Duane E.
Hsu Wei-Yung
Hwang Ming
Lu Jiong-Ping
Bowers Charles
Brady Wade James
Donaldson Richard L.
Garner Jacqueline J.
Lee Hsien Ming
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