SRAM memory circuit and method of operation therefor

Details SRAM memory circuit and method of operation therefor SRAM memory circuit and method of operation therefor

1996-10-24

1997-09-23

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365175, G11C 1136

Patent

active

056711824

ABSTRACT:
A memory array circuit has two memory sections. Each memory section has a matrix of column lines and row lines. A plurality of storage latches are arranged in the matrix, with each storage latch having a data node, and a voltage node. Each of the plurality of storage latches has an associated column line and an associated row line, with the voltage node connected to the associated row line. A diode connects the data node of a storage latch to its associated column line. A first decoder decodes a first address signal and selects one of the column lines. A second decoder decodes a second address signal, and generates a row output signal, with each row output signal of the second decoder having a corresponding row line. A plurality of voltage control circuits is provided with each voltage control circuit receiving one of the plurality of row output signals, and for applying a control signal to a corresponding row line, in response to a data read signal, a data write to one state signal or a data write to another state signal. A plurality of sense amplifiers differentially senses corresponding column lines of the two memory sections.

REFERENCES:
patent: 3986173 (1976-10-01), Baitinger et al.
patent: 4247918 (1981-01-01), Iwashashi et al.
patent: 5063539 (1991-11-01), Rallapalli
patent: 5535156 (1996-07-01), Levy et al.
"Pinch Load Resistors Shrink Bipolar Memory Cells" by S.K. Wiedmann, Electronics, Mar. 7, 1974, pp. 130-133.

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