SRAM layout for relaxing mechanical stress in shallow trench iso

Details SRAM layout for relaxing mechanical stress in shallow trench iso SRAM layout for relaxing mechanical stress in shallow trench iso

1999-02-18

2000-09-12

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438296, 257776, H01L 218234

Patent

active

061177229

ABSTRACT:
An SRAM device has STI regions separated by mesas and doped regions including source/drain regions, active areas, wordline conductors and contacts in a semiconductor substrate is made with a source region has 90.degree. transitions in critical locations. Form a dielectric layer above the active areas. Form the wordline conductors above the active areas transverse to the active areas. The source and drain regions of a pass gate transistor are on the opposite sides of a wordline conductor. Form the sidewalls along the <100> crystal plane. Form the contacts extending down through to the dielectric layer to the mesas. Substrate stress is reduced because the large active area region formed in the substrate assures that the contacts are formed on the <100> surfaces of the mesas are in contact with the mesas formed on the substrate and that the <110> surfaces of the silicon of the mesas are shielded from the contacts.

REFERENCES:
patent: 5466632 (1995-11-01), Lur et al.
patent: 5914504 (1999-06-01), Augusto
patent: 5977558 (1999-11-01), Lee
patent: 6043562 (2000-03-01), Keeth

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