SRAM design with separated VSS

Details SRAM design with separated VSS SRAM design with separated VSS

2007-03-02

2008-12-16

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S226000

Reexamination Certificate

active

07466581

ABSTRACT:
An array of static random access memory (SRAM) cells arranged in a plurality of rows and a plurality of columns includes a plurality of VSS lines connected to VSS nodes of the SRAM cells, with each VSS line connected to the SRAM cells in a same column. The plurality of VSS lines includes a first VSS line connected to a first column of the SRAM cells; and a second VSS line connected to a second column of the SRAM cells, wherein the first and the second VSS lines are disconnected from each other.

REFERENCES:
patent: 6417032 (2002-07-01), Liaw
patent: 6569723 (2003-05-01), Liaw
patent: 6985380 (2006-01-01), Khellah et al.
patent: 2005/0146913 (2005-07-01), Madan
patent: 2007/0025162 (2007-02-01), Deng et al.
patent: 2007/0076467 (2007-04-01), Yamaoka et al.
patent: 2008/0031045 (2008-02-01), Liaw
Zhang, K., et al., A 3-GHZ 70-Mb SRAM in 65-nm CMOS Technology With Integrated Column-Based Dynamic Power Supply, IEEE Journal of Solid-State Circuits, Jan. 2006, pp. 146-151, vol. 41, No. 1, IEEE.

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