Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
2007-06-19
2007-06-19
Hur, J. H. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S189090, C365S189011, C365S154000
Reexamination Certificate
active
11282273
ABSTRACT:
A merged structure SRAM cell is provided that includes a first transistor and a second transistor. The second transistor gate forms a load resistor for the first transistor and the first transistor gate forms a load resistor for the second transistor. Also provided is a method of reading a memory cell that comprises applying a potential difference (VDIFF) to a selected memory cell by providing a column line potential (VC) and a row line potential (VR). According to this method, VDIFFis increased by an increment less than a transistor threshold voltage (VT). It is then determined whether the increased VDIFFresults in a current flow on the column line for the selected memory cell. Also provided is a method of writing a memory cell that comprises applying VDIFFand increasing VDIFFby an increment more than VTto set the selected memory cell to a one state.
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Hur J. H.
Micro Technology Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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