Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-05-22
2002-08-13
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S482000, C438S166000
Reexamination Certificate
active
06432804
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to polysilicon thin film transistor (TFT) technology, and specifically to a process for manufacturing such devices.
BACKGROUND OF THE INVENTION
Thin film transistors (TFTs) are usually applied to liquid crystal displays (LCDs). This technology is also applicable to other devices, such as IC, X-ray imaging technology and sensor arrays, as well as specific products or product concepts, such as sheet computers, sheet phones, sheet recorders, etc.
Polysilicon TFTs are made by a variety of processes. The usual manner of constructing a polysilicon TFT LCDs is by a process known as top-gate. The process steps for this structure include: (1) depositing an amorphous silicon (a-Si) precursor; (2) dehydrogenation; (3) impurity doping to control Vth (threshold voltage) of the TFTs; (4) crystallization of amorphous silicon to polysilicon; (5) insulator deposition; (6) gate electrode formation; (7) impurity doping for the formation of low resistance source/drain regions; (8) activation of doped impurity; (9) hydrogenation; (10) interlayer formation; (11) source and drain contact hole etching; and (12) source and drain metal contact formation.
Typically, plasma-enhanced chemical vapor deposition (PE-CVD) or low-pressure CVD (LP-CVD) is used to deposit the amorphous silicon precursor. There are several advantages in using physical vapor deposition (PVD), i.e., sputtering, to form the silicon film. Such advantages are process reduction, i.e., no need for dehydrogenation, equipment cost reduction and improved process safety, because no toxic/pyrophoric gases are necessary. The additional advantage of PVD process is in the area of Vth control by impurity doping. This is a required process, regardless of the method chosen for the deposition of amorphous silicon.
U.S. Pat. No. 5,248,630 to Serikawa et al., for Thin film silicon semiconductor device and process for producing thereof, granted Sep. 28, 1993, describes a technique for forming a thin film silicon device.
U.S. Pat. No. 5,817,550 to Carey et al., for Method for formation of thin film transistors on plastic substrates, granted Oct. 6, 1998, describes the low-temperature formation of TFTs on a polymer substrate.
SUMMARY OF THE INVENTION
A method of forming a thin film device includes preparing a substrate; forming a silicon target having predetermined impurities therein; depositing a layer of amorphous silicon by physical vapor deposition from the target; and crystallizing the amorphous silicon layer to form a polysilicon layer. The method of the invention is particularly suited to the formation of thin film transistors and liquid crystal displays incorporating thin film transistors.
An object of the invention is to provide a target for a PVD process wherein the target is doped with specific impurities to deposit an active layer on a substrate.
A further object of the invention is to form a TFT wherein deposition of an amorphous silicon film is combined with impurity doping.
Another object of the invention is to form a TFT device where threshold voltage adjustment is achieved using fewer steps than required by the prior art.
This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention. A more thorough understanding of the invention may be obtained by reference to the following detailed description of the preferred embodiment of the invention in connection with the drawings.
REFERENCES:
patent: 5072264 (1991-12-01), Jones
patent: 5248630 (1993-09-01), Serikawa et al.
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patent: 5424244 (1995-06-01), Zhang et al.
patent: 5488000 (1996-01-01), Zhang et al.
patent: 5559042 (1996-09-01), Yamazaki et al.
patent: 5817550 (1998-10-01), Carey et al.
patent: 6268272 (2001-07-01), Jang
patent: 6284635 (2001-09-01), Jang
Hartzell John
Nakata Yukihiko
Voutsas Apostolos
Krieger Scott C.
Le Dung Anh
Nelms David
Rabdau Matthew D.
Ripma David C.
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