Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2000-10-12
2004-03-16
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S787000, C438S790000
Reexamination Certificate
active
06706646
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a spin-on glass (SOG) composition useful in forming a silicon oxide layer in a semiconductor manufacturing process, to a semiconductor device made thereby, and to a method of forming a silicon oxide layer using the same. More particularly, the present invention relates to a spin-on glass composition containing perhydropolysilazane, and its use in forming a silicon oxide layer in a semiconductor device.
2. Description of the Related Art
The design of semiconductor devices have recently made rapid progress. In particular, this progress has required semiconductor devices to function with high operating speed, and to have a large storage capacitance. In order to satisfy such requirements, semiconductor devices with increased density, reliability, and response time are under development.
Integrated circuits typically are manufactured by forming a large number of active devices on a single substrate. After each device is formed and insulated, some of the devices are electrically interconnected during the manufacturing process to accomplish a desirable circuit function. Metal Oxide Semiconductor (MOS) and bipolar VLSI and ULSI devices, for example, have multilevel interconnection structures in which a large number of devices are interconnected. In such a multilevel interconnection structure, the topography of the top layer usually is increasingly irregular and uneven as the number of layers increases.
For example, a semiconductor wafer with two or more metal layers typically is formed as follows. A number of oxide layers, a polycrystalline silicon conductive layer, and a first metal wiring layer are formed on a semiconductor wafer. A first insulation layer then is formed on the resulting structure. Then, a via hole is formed for providing circuit paths to a second metal layer. At this time, the surface of the first insulation layer is uneven because the layers underlying the first insulation layer are uneven. When the second metal layer is directly formed on the first insulation layer, the second metal layer may fracture due to protrusions or cracks in the underlying insulation layer. In addition, there may be a decreased yield of the semiconductor device if the deposition state of the metal layer is poor. Accordingly, the insulation layer typically is planarized before formation of the via hole or the second metal layer that will be formed in a multilevel metal interconnection structure to offset the effects of a varied wafer topography.
Various methods have been developed to planarize the insulation layer. These methods include utilizing a borophosphorous silicate glass (BPSG) layer, which has good reflow characteristic, or an SOG layer and a chemical mechanical polishing (CMP) method. In general, BPSG is widely utilized as an insulation layer material to fill gaps between metal wirings. However, depositing BPSG presents problems because it depends primarily on establishing special deposition parameters for the equipment utilized. In addition, the gases used in the process are expensive and severely toxic.
Furthermore, as the packing density increases and the design rule gradually decreases for manufacturing VLSI having 256 megabits or more, using BPSG as the insulation layer to fill gaps between wirings lowers the yield due to the occurrence of voids and bridges. In addition, an etch stop layer may possibly be damaged during its subsequent formation. Thus, the prior art typically implements a reflowing process and an expensive CMP process to solve these problems.
An insulation layer formed by an SOG layer is known as being manufactured by a simple coating process. This process produces a planar insulation layer. For example, U.S. Pat. No. 5,310,720 (issued to Shin et al.) discloses a method for making a silicon oxide layer. A polysilazane layer is formed, and then the polysilazane layer is heated in an oxygen atmosphere to convert it into a silicon oxide layer. U.S. Pat. No. 5,976,618 (issued to Shunichi Fukuyama et al.) discloses a method in which an inorganic SOG is deposited, and then two step heat treatment processes are implemented to convert the SOG layer into a silicon oxide layer.
The basic backbone structure of polysilazane-based SOG is composed of Si—N. Si—H and N—H bonds. The Si—N bonds are converted into (or substituted with) Si—O bonds by baking under an atmosphere including oxygen and water. A simple spin coating and a simple curing process are performed to convert the SOG layer into the silicon oxide layer. Accordingly, it is an economical method.
However, not all of the Si—N bonds are converted to Si—O bonds (see, for example. Japanese Patent Laid-Open No. Hei 11-145286). Accordingly, the silicon oxide layer has different insulating and electrical characteristics when compared to a pure silicon oxide layer such as one formed using a BPSG layer or a TEOS layer. For these reasons, many have avoided using the conventional SOG layer and then converting it into a silicon oxide insulation layer. In addition, because SOG is deposited by a spin coating method, the thickness of the thus formed silicon oxide layer is not sufficient. This provides insufficient coverage for the conductive layers, such as gate electrodes and metal wirings.
SUMMARY OF THE INVENTION
Accordingly, it is a feature of an embodiment of the present invention to provide a spin-on glass composition that fills gaps between closely-spaced metal wirings of semiconductor devices having a high packing density and a large aspect ratio. It is also a feature of the present invention to provide a composition that fills gaps or smoothes surface discontinuities on a substrate without the need for mechanical planarization. It also is a feature of the invention to provide a spin-on glass composition that has substantially the same characteristics as an oxide layer of a semiconductor device formed by a chemical vapor deposition (CVD) method. It is another feature of the invention to provide a method of forming an oxide layer in a semiconductor manufacturing process using the above spin-on glass composition.
In accordance with these and other features of the invention, there is provided a spin-on glass composition and device made therewith containing perhydropolysilazane having the formula —(Si
2
NH)
n
— wherein n represents a positive integer, in an amount of about 10 to about 30% by weight based on the total weight of the composition, whereby the perhydropolysilazane has a weight average molecular weight within the range of about 4,000 to about 8,000, and a molecular weight dispersion within the range of about 3.0 to about 4.0. The spin-on glass composition of the invention also includes a solvent in an amount of about 70% to about 90% by weight, based on the total weight of the composition.
In accordance with another feature of the invention, there is provided a method of forming a silicon oxide layer on a semiconductor substrate having a stepped portion or surface discontinuities. The method entails coating on the semiconductor substrate a spin-on glass composition containing the compound perhydropolysilazane having the chemical formula —(SiH
2
NH)
n
— wherein n represents a positive integer, a weight average molecular weight within the range of about 4,000 to 8,000, and a molecular weight dispersion within the range of about 3.0 to 4.0, thereby forming a planar SOG (spin-on glass) layer. Finally, the SOG layer is cured to form a silicon oxide layer having a planar surface. The invention further includes a semiconductor device made by the aforementioned method.
According to various embodiments of the present invention, a uniform silicon oxide layer having substantially no voids can be formed by utilizing an SOG composition that completely covers a conductive layer having an aspect ratio of about 5:1 to 10:1 or other surface discontinuities.
REFERENCES:
patent: 4937304 (1990-06-01), Ayama et al.
patent: 4950381 (1990-08-01), Takeuchi et al.
patent: 5436398 (1995-07-01), Shimizu et al.
patent: 5494978 (1996-02-01), Shimizu et al
Choi Jung-Sik
Chon Sang-Mun
Kang Dae-Won
Kim Hong-Ki
Lee Dong-Jun
Coleman W. David
Lee & Sterba, P.C.
Nguyen Khiem D
Samsung Electronics Co,. Ltd.
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