Spacers with a graded dielectric constant for semiconductor...

Details Spacers with a graded dielectric constant for semiconductor... Spacers with a graded dielectric constant for semiconductor...

2002-02-27

2004-07-20

Ghyka, Alexander (Department: 2812)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S578000, C438S582000, C438S758000

Reexamination Certificate

active

06764966

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to semiconductor devices having a dielectric layer of a high-K material. In particular, the present invention relates to spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric.
BACKGROUND
A conventional field effect transistor (FET) is characterized by a vertical stack on a semiconductor substrate. The semiconductor substrate is doped with either n-type or p-type impurities to form an active region in the semiconductor substrate. The vertical stack includes a gate dielectric and a gate electrode. The gate dielectric of silicon dioxide (SiO
2
gate dielectric), for example, is formed on the semiconductor substrate. The gate electrode of polysilicon, for example, is formed on the gate dielectric. The gate electrode formed on the SiO
2
gate dielectric defines a channel interposed between a source and a drain formed within the active region of the semiconductor substrate. The source and the drain are formed by dopant impurities introduced into the semiconductor substrate. Spacers of SiO
2
, for example, are formed on the sidewalls of the vertical stack.
A pervasive trend in modern integrated circuit manufacture is to produce semiconductor devices, e.g., FETs, having featured sizes as small as possible. Many present processes employ features, such as gate electrodes and interconnects, which have less than a 0.18 &mgr;m critical dimension. As feature sizes continue to decrease, the size of the resulting semiconductor device, as well as the interconnect between semiconductor devices, also decreases. Fabrication of smaller semiconductor devices allows more semiconductor devices to be placed on a single monolithic semiconductor substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area.
As semiconductor device feature sizes decrease, the thickness of the SiO
2
gate dielectric decreases as well. This decrease in SiO
2
gate dielectric thickness is driven in part by the demands of overall device scaling. As gate electrode widths decrease, for example, other device dimensions must also decrease in order to maintain proper device operation. Early semiconductor device scaling techniques involved decreasing all dimensions and voltages by a constant scaling factor, to maintain constant electric fields in the device as the feature size decreased. This approach has given way to more flexible scaling guidelines which account for operating characteristics of short-channel devices. A maximum value of semiconductor device subthreshold current can be maintained while feature sizes shrink. Any or all of several quantities may be decreased by appropriate amounts including SiO
2
gate dielectric thickness, operating voltage, depletion width and junction depth, for example.
As a result of the continuing decrease in feature size, SiO
2
gate dielectric thickness has been reduced so much that SiO
2
layers of the SiO
2
gate dielectrics are approaching thicknesses on the order of ten angstroms (Å). Unfortunately, thin SiO
2
layers may break down when subjected to an electric field, particularly SiO
2
layers of the gate dielectrics less than 50 angstroms (Å) thick. It is probable that even for a relatively low gate voltage of 3V, electrons can pass through such thin SiO
2
layers by a quantum mechanical tunneling effect. In this manner, a leakage current may undesirably form between the gate electrode and the semiconductor substrate, adversely in affecting the operability of the device. For example, the leakage current changes from 1×10
−12
angstroms/cm
2
to 1×10 angstroms/cm
2
for ~35 angstroms (Å) and ~15 angstroms (Å) thick SiO
2
layers, respectively, at gate bias of ~1V. In other words, the leakage current increases about 12 orders of magnitude for about a two-fold decrease in thickness. The exponential increase in the SiO
2
layer leakage current significantly affects the operation of semiconductor devices, particularly with regard to standby power, dissipation, reliability and lifetime.
One proposed solution is to replace the SiO
2
material of the gate dielectric with a material having a dielectric constant value higher than SiO
2
(high-K dielectric material will be further explained below). Using a dielectric material having a high-K for the gate dielectric would allow a higher capacitance and an electric equivalent thickness of a thinner SiO
2
gate dielectric to be achieved while maintaining or increasing the physical thickness of the gate dielectric. For example, an aluminum oxide (Al
2
O
3
) layer with a K of 9.6 and a physical thickness of 62.5 angstroms (Å) is substantially electrically equivalent to a SiO
2
layer (K=3.9) having a physical thickness of 25 angstroms (Å). Thus, the gate dielectric of Al
2
O
3
would have an electrical equivalent thickness of 25 angstroms (Å) of SiO
2
, but have a physical thickness of 62.5 angstroms (Å). Therefore, the gate dielectric can be made electrically thin while being formed of a physically thicker layer. As a result, further device scaling can be achieved.
However, the SiO
2
spacers of a FET with the high-K gate dielectric may form a fixed charge in the SiO
2
spacers near an interface adjacent the gate dielectric. The fixed charge may form due to a tunneling of electrons into the spacers near the interface of the gate dielectric and the high-K gate dielectric due to the difference in the dielectric constant of the materials. Further, the SiO
2
spacers may entrap some electrons due to, for example, dangling bonds. As a result, a net negative charge density may form in the SiO
2
spacers as described above. As the trapped charge accumulates with time, the operation of the device will be degraded. A fixed charge may also be formed in a dielectric material having a lower dielectric constant during the processing of the semiconductor device.
Therefore, there exists a strong need in the art for a spacer with a graded dielectric constant in order to inhibit the formation of the fixed charge in the spacer of a semiconductor device having a high-K dielectric material.
SUMMARY OF THE INVENTION
A spacer having a graded dielectric constant may be formed which will inhibit the formation of a fixed charge in the spacer near the interface of a gate dielectric of a high-K dielectric material of a semiconductor device. The spacer would include at least one layer of a high-K material (e.g., a first layer) and at least one layer of a material having a dielectric constant less than the first layer (e.g., a second layer). The first layer of the spacer would be of a high-K material having a dielectric constant equal to or greater than the dielectric constant of the high-K gate dielectric. The second layer, and any subsequent layer, of the spacer would be of a dielectric constant material having a dielectric constant less than the preceding layer. The first layer of high-K material adjacent the high-K gate dielectric will reduce the probability of the electrons tunneling into the spacer and becoming entrapped by the first layer of the spacer adjacent the gate dielectric. Thus, the formation of a fixed charge found in a conventional SiO
2
spacer can be removed to a region of the graded dielectric constant spacer in which the fixed charge will not affect the operability of the semiconductor device. Therefore, the operability of the semiconductor device can be improved through further device scaling using high-K materials for gate dielectrics resulting in smaller, faster, more reliable devices.
According to one aspect of the invention, the invention is a semiconductor device formed on a semiconductor substrate having an active region. The semiconductor device includes a dielectric layer interposed between a gate electrode and the semiconductor substrate. Further, the semiconductor device includes graded dielectric constant spacers formed on sidewalls of the dielectric layer, sidewalls of the gate electrode and portions of an upper surface

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