Active solid-state devices (e.g. – transistors – solid-state diode – Including semiconductor material other than silicon or... – Containing germanium – ge
Reexamination Certificate
2002-03-11
2003-02-11
Ngô, Ngâan V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Including semiconductor material other than silicon or...
Containing germanium, ge
C438S154000, C438S164000, C257S347000
Reexamination Certificate
active
06518645
ABSTRACT:
RELATED APPLICATION
This application relies for priority upon Korean Patent Application No. 2001-16834, filed on Mar. 30, 2001, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention generally relates to a semiconductor device using an SOI-type semiconductor substrate and a method of forming the semiconductor device. More specifically, the present invention is directed to a semiconductor substrate for suppressing a floating body effect (FBE) phenomenon that occurs as devices formed in an SOI-type substrate are fully isolated from one another and a method of forming the semiconductor device.
BACKGROUND OF THE INVENTION
In semiconductor device fabrication, a number of devices are formed on a silicon wafer surface and are electrically connected through interconnections. Isolation devices are formed in a narrow region so as not to interfere with peripheral devices. To avoid such interference, impurity junctions and device isolation layers are employed. As semiconductor devices undergo further integration, the distance between devices to be isolated becomes smaller. Conventional device isolation layers therefore no longer meet the requirements for sufficient isolation.
A junction-type device isolation approach is not suitable for a semiconductor device employing a high voltage device in that a resisting pressure at the junction surface is limited. Also, the junction-type device isolation method is not suitable in a high radioactive environment because current is created at the junction depletion surface by radioactive rays such as gamma rays.
For overcoming such disadvantages, a semiconductor device using an SOI-type substrate was suggested, in which a buried oxide layer is formed under a silicon layer in which devices are formed. Particularly, a high performance semiconductor device such as a central processing unit (CPU) commonly employs an SOI-type semiconductor device in which a device region is completely isolated by an insulating layer.
Referring now to
FIG. 1
, a device isolation layer
112
or the like is formed on an SOI-type substrate in which a lower silicon layer
100
, a buried oxide layer
110
, and an SOI layer are stacked. Following the device isolation step, the SOI layer constitutes a semiconductor device body
122
at each isolated region that is divided by the buried oxide layer
110
and the device isolation layer
112
. Namely, the body
122
is completely electrically floated by lower and lateral insulating layers, which is an original purpose of the SOI substrate. Unfortunately, a floating body may cause various side effects. For example, when a voltage is applied to a gate electrode in an NMOSFET transistor to make current flow from a drain region
116
to a source region
114
through a channel region
120
, atoms constituting the body collide with electrons to generate pairs of hole-electrons, which accumulate in the floating body. Holes generated in a semiconductor device using a conventional bulk substrate can be removed through a ground line coupled to the substrate. However, in the floating device, holes continuously accumulate around the center of the low potential region (i.e., the lower portion of the interface between the source region
114
and the channel region
120
) that form the isolated semiconductor layer in each area of the SOI-type semiconductor device. The accumulated holes serve to heighten the channel potential and lower the threshold voltage, thereby altering the drain voltage-current characteristic such as a kink effect.
Assuming that the holes are intensively accumulated, the body layer including the channel between source and drain regions forms a P-type impurity region. Therefore, the P-type impurity region constitutes a form of NPN-type bipolar transistor together with the N-type impurity regions forming a source and drain (parasitic bipolar action). Arising from this phenomenon, the breakdown voltage of the transistor device is lowered, which adversely impacts normal device operation. Furthermore, assuming the accumulated holes are coupled to electrons that constitute a portion of the current for operating a transistor when a specific operation current flows, the coupling causes a form of a leakage current that can result in operating errors.
For that reason, special ground means for removing holes accumulated at each region of a semiconductor device using a SOI-type substrate are utilized. One example of such ground means is to form a contact coupled to a partial body region (the region where source-channel interface holes are accumulated), the contact in turn being connected to a ground line. In view of this, a contact region
130
must be added to existing active regions such as source/drain regions
114
and
116
and a channel region, as shown in FIG.
3
. In this case, the contact forming region is extendedly formed at a hole accumulating portion of the device. The source/drain regions
114
and
116
are surrounded by a device isolation layer
112
, and are divided by a gate electrode
118
. The existing shape of the device region is therefore changed for forming the contact and the corresponding ground line. Unfortunately, arising from this change in shape, device integration density is reduced and parasitic capacitance is increased. In addition, processing costs are increased.
With reference to
FIGS. 4 and 5
, another means for forming the ground contact involves formation of a ground region
230
around an existing device region
222
independent therefrom. A shallow trench isolation layer
212
is formed so that a bottom side of a device isolation layer
220
does not contact a buried oxide layer at the connecting portion
220
that is a part of a device isolation layer forming an interval between the device region
222
and a ground region
230
. Thus, a body of the device region
222
is linked with a body of the ground region
230
through an SOI layer that is positioned at a gap between a shallow trench isolation layer
212
and a lower buried oxide layer
110
. Accumulated holes, which are generated from the device region
222
, are drained to the exterior through the ground region
230
, a contact plug
232
, and a ground interconnection
234
. When such a body linked structure is applied to a semiconductor device, a large body width of a device region and a large channel width of a MOS transistor make it difficult to readily drain holes that are accumulated at a distant position from the connecting part.
In order to readily drain holes under a shallow trench isolation layer, it is preferable that a concentration of P-type impurities is high at a connecting semiconductor layer to operate as a hole passage between a bottom side of a partial trench isolation layer of a connecting part and a buried oxide layer. When boron ions are introduced into the connecting part as P-type impurities, they are easily diffused to peripheral buried oxide layer or trench isolation layer. This lowers the concentration of the boron impurities, which, in turn, operates as an impediment to removal of the holes.
SUMMARY OF THE INVENTION
The present invention addresses the above-identified problems resulting from the floating body phenomenon of the SOI-type semiconductor device.
It is an object of the present invention to provide an SOI-type semiconductor device capable of achieving high speed operation and precise device isolation, while preventing device operation error which results from a floating body phenomenon.
It is another object of the present invention to provide an SOI-type semiconductor device capable of effectively draining holes accumulated at the body of an isolated NMOS transistor device region.
It is still another object of the present invention to provide a method of forming the foregoing SOI-type semiconductor devices.
In a first aspect, the present invention is directed to a silicon-on-insulator(SOI)-type semiconductor device including a lower silicon layer, a buried oxide layer, and an SOI layer. The device comprises a device region isolated by
Bae Geum-Jong
Choe Tae-Hee
Kim Sang-Su
Rhee Hwa-Sung
Mills & Onello LLP
Ngô Ngâan V.
Samsung Electronics Co,. Ltd.
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