Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-11-15
2005-11-15
Thompson, Craig A. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06964897
ABSTRACT:
A DRAM array in an SOI wafer having a uniform BOX layer extending throughout the array eliminates the collar oxide step in processing; connects the buried plates with an implant that, in turn, is connected to a conductive plug extending through the device layer and the box that is biased at ground; while the pass transistors are planar NFETs having floating bodies that have a leakage discharge path to ground through a grounded bitline.
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Bard Karen A.
Dobuzinsky David M.
Ho Herbert L.
Kumar Mahendar
Pendleton Denise
Harrison Monica D.
Petraske Eric W.
Thompson Craig A.
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