Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-11-21
2003-12-30
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S356000, C257S358000, C257S360000, C257S371000
Reexamination Certificate
active
06670677
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and to a method of fabricating the same. More particularly, the present invention relates to a silicon-on-insulator (SOI) integrated circuit having an electrostatic discharge (ESD) circuit and to a method of fabricating the same.
2. Description of the Related Art
Generally, a semiconductor device includes an electro-static discharge (ESD) circuit for protection. Thus, a semiconductor device can endure several thousand volts applied instantaneously from external sources. The ESD circuit has a function of protecting an internal circuit by bypassing static charges injected into each pad, through a power pad or a ground pad, in the event that a voltage deviating from the range of operating voltage is applied to each pad.
Problems with silicon substrates, which are widely used as substrates for semiconductor devices, however, can render forming an ESD circuit difficult for reasons that will follow.
First, forming shallow source/drain regions of a transistor is difficult making it not only difficult to realize highly integrated semiconductor devices, but also to decrease parasitic capacitance between the silicon substrate and the source/drain regions. Consequently, it is difficult to obtain improvements in the operation speed of semiconductor devices. Second, when forming a semiconductor memory device at a silicon substrate, it is difficult to decrease a soft error rate (SER) due to the cell-formed well. Third, when fabricating a semiconductor device having a CMOS circuit, it is difficult to suppress latch-up phenomenon.
Recently, in response to the above-mentioned problems associated with forming a semiconductor device at a silicon substrate, a technique of fabricating a semiconductor integrated circuit at a SOI substrate has been widely used. However, there are still limitations on the formation of an ESD circuit when fabricating a semiconductor device at a SOI substrate
FIG. 1
illustrates an equivalent circuit design of a typical SOI integrated circuit having an ESD circuit.
Referring to
FIG. 1
, an input pad
50
is connected with an internal circuit
100
through an ESD circuit
1
. The ESD circuit
1
includes a diode D. The ESD circuit
1
may also include a MOS transistor. A n-type region and a p-type region of the diode are connected with the input pad
50
and a ground terminal, respectively. Also, the input pad
50
is connected with an input terminal of the internal circuit
100
. The input terminal of the internal circuit
100
corresponds to a gate electrode of the MOS transistor composing a CMOS circuit. Although an inverter including both a PMOS transistor Tp and an NMOS transistor Tn is given here as an example of the internal circuit, the internal circuit may be a circuit including a NAND gate, a NOR gate or a combination thereof.
Reverse bias breakdown voltage of the diode D should be higher than the operating voltage of the internal circuit
100
, that is, power voltage. Also, reverse bias breakdown voltage of the diode D should be lower than the gate oxide layer breakdown voltage of both the PMOS transistor Tp and the NMOS transistor Tn composing the internal circuit
100
.
When applying voltage higher than the reverse bias breakdown voltage of the diode D to the input pad
50
, a large current is by-passed to the ground terminal through the diode D. Thus, although a high voltage of several thousand volts is applied to the input pad
50
, a voltage, which is applied to the input terminal of the internal circuit, is higher than the power voltage and lower than the gate oxide layer breakdown voltage. Thus, the internal circuit
100
is protected by the ESD circuit
1
.
FIGS. 2 through 4
illustrate cross-sectional views of a conventional fabrication method for realizing the SOI integrated circuit shown in FIG.
1
.
Referring to
FIG. 2
, a SOI substrate is prepared. The SOI substrate includes a supporting substrate
11
, a buried oxide layer
13
stacked on the supporting substrate
11
and a semiconductor layer
15
stacked on the buried oxide layer
13
. A device isolation layer
15
a
is selectively formed at a predetermined region of the semiconductor layer
15
. The device isolation layer
15
a
is formed to contact with the buried oxide layer
13
. Thus, active regions
15
b
surrounded by the device isolation layer
15
a
and the buried oxide layer
13
are defined. A photoresist pattern
17
is formed on the resultant structure where the device isolation layer
15
a
is formed. The photoresist pattern
17
has a first opening
17
a
and a second opening
17
b
exposing predetermined regions of the ESD circuit region
1
.
Referring to
FIG. 3
, the device isolation layer
15
a
and the buried oxide layer
13
are continuously dry-etched using the photoresist pattern
17
of
FIG. 2
as an etch mask, to form holes exposing predetermined regions of the supporting substrate
11
. At this time, the exposed supporting substrate
11
has a damaged surface
21
resulting from the dry-etch. Epitaxial layers are selectively formed on the damaged surface
21
. Thus, because a property of the semiconductor epitaxial layers is that they are directly affected by the underlying layer, first and second semiconductor epitaxial layers
19
a
and
19
b
have crystalline defects.
Referring to
FIG. 4
, the NMOS transistor Tn and the PMOS transistor Tp of
FIG. 1
are formed at the active regions
15
b
in the internal circuit region
100
using a conventional method. The NMOS transistor includes both a gate oxide layer
21
and a first gate electrode
23
n
sequentially stacked on a predetermined region of the active region
15
b
. Further, the NMOS transistor includes a first source region
27
s
and a first drain region
27
d
formed at both sides of the first gate electrode
23
n
, respectively. Likewise, the PMOS transistor includes a gate oxide layer
21
and a second gate electrode
23
p
sequentially stacked on a predetermined region of the active region adjacent to the NMOS transistor. The PMOS transistor also includes a second source region
29
s
and a second drain region
29
d
formed at both sides of the second gate electrode
23
p
, respectively.
Further, spacers
25
are formed on sidewalls of the first and second gate electrodes
23
n
and
23
p
. Also, metal silicide layers
31
may be formed on the first and second gate electrodes
23
n
and
23
p
, and the first and second source/drain regions
27
s
,
27
d
,
29
s
and
29
d
, through a self-aligned silicide (salicide) process.
Meanwhile, a p-type impurity layer
29
p
and an n-type impurity layer
27
p
are formed in the first and second semiconductor epitaxial layers
19
a
and
19
b
of
FIG. 3
, respectively. The n-type impurity layer
27
p
may be formed simultaneously with the first source/drain regions
27
s
and
27
d
, and the p-type impurity layer
29
p
may be formed simultaneously with the second source/drain region
29
s
and
29
d
. Also, the metal silicide layers
31
may be formed even at the surfaces of the n-type and p-type impurity layers
27
p
and
29
p
. The n-type and p-type impurity layers
27
p
and
29
p
correspond to the n-type and p-type regions of the diode D illustrated in
FIG. 1
, respectively. Consequently, a junction of the diode D exists in the semiconductor epitaxial layers
19
a
and
19
b
, and thus, the diode shows a very inferior leakage current characteristic.
According to the conventional technology as described above, the leakage current characteristic of the diode used as the ESD circuit becomes remarkably lowered. Thus, the ESD characteristic of the SOI integrated circuit is degraded.
SUMMARY OF THE INVENTION
It is therefore a feature of an embodiment of the present invention to provide a SOI substrate having an etch stopping layer interposed between a buried oxide layer and a supporting substrate.
It is another feature of an embodiment of the present invention to provide a SOI integrated circuit having an improved ESD characteristic by forming an ESD
Bae Geum-Jong
Choe Tae-Hee
Kim Sang-Su
Lee Nae-In
Rhee Hwa-Sung
Lee & Sterba, P.C.
Samsung Electronics Co,. Ltd.
Wojciechowicz Edward
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