Snapback reduces the electron and hole trapping in the tunneling

Details Snapback reduces the electron and hole trapping in the tunneling Snapback reduces the electron and hole trapping in the tunneling

1997-10-14

1998-10-27

Dinh, Son T.

Static information storage and retrieval

Floating gate

Particular biasing

36518518, 365218, G11C 1604

Patent

active

058286055

ABSTRACT:
The present invention provides method to erase flash EEPROMS devices using a positive sine waveform (Vs) and negative Vg that drives a cell in to snapback breakdown to remove trapped electron in the tunnel oxide and improve device performance. The snapback breakdown operation of one cell in the array lowers the tunnel oxide electric field for all cells in the array. The snapback breakdown generates a substrate current that reduces the electric field thereby reducing electron and hole trapping. The method comprises the steps of: (a) applying a positive sine waveform voltage (Vs) to a source region of said EEPROM device during an entire erase cycle; (b) grounding a well region of said EEPROM device during an entire erase cycle; (c) grounding a drain region of said EEPROM device during an entire erase cycle; (d) simultaneously applying a negative voltage (Vg) to a control gate of said EEPROM device during the entire erase cycle; and whereby the positive sine waveform to the source region reduce the electric field in a tunnel oxide layer which reduces the electron and hole trapping.

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Feng et al. "MOSFET Drain Breakdown Voltage", IEEE device letters vol. EDL-7 No. 7, Jul. 1986, pp. 449-450.

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