Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1996-03-22
2000-06-20
Nelms, David
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438639, 438643, 438672, 438680, 438686, H01L 2144
Patent
active
060777818
ABSTRACT:
The present invention relates generally to an improved apparatus and process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron aperture width applications. In one aspect of the invention, a dielectric layer is formed over a conducting member. A thin nucleation layer is then deposited onto the dielectric layer prior to etching high aspect ratio apertures through the nucleation and dielectric layers to expose the underlying conducting member on the aperture floor. A CVD metal layer is then deposited onto the structure to achieve selective deposition within the apertures, while preferably also forming a blanket layer on the field. The present apparatus and process reduce the number of steps necessary to fabricate CVD metal interconnects and layers that are substantially void-free and planarized. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the apertures to form vias and contacts occurs without the formation of oxides between the layers.
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Chen Liang-Yuh
Guo Ted
Mosely Roderick C.
Naik Mehul
Applied Materials Inc.
Berry Renee R.
Nelms David
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