Coating processes – Nonuniform coating – Mask or stencil utilized
Reexamination Certificate
1998-12-07
2001-05-29
Talbot, Brian K. (Department: 1762)
Coating processes
Nonuniform coating
Mask or stencil utilized
C427S097100, C427S103000, C427S123000, C427S126100, C427S402000, C101S123000, C101S129000
Reexamination Certificate
active
06238741
ABSTRACT:
RELATED APPLICATION
This application is related to Buechele et al. U.S. Patent Application Ser. No. 09/206,158 now U.S. Pat. No. 6,062,135 entitled “A SCREENING APPARATUS INCLUDING A DUAL RESERVOIR DISPENSING ASSEMBLY” (IBM Docket No. FI9-98-159), filed even date herewith, the disclosure of which is incorporated by reference herein.
BACKGROUND OF THE INVENTION
This invention relates to electronic substrates, and more particularly, relates to ceramic and organic substrates having multilayer features thereon for electronics packaging applications and a method for forming such multilayer features.
Glass, ceramic and glass ceramic (hereafter just ceramic) and organic structures are used in the production of electronic substrates and devices for electronics packaging applications. Many different types of structures can be used. For example, a multilayered ceramic circuit substrate may comprise patterned metal layers which act as electrical conductors sandwiched between ceramic layers which act as insulators. Organic substrates, also coalled printed circuit boards, may be single layer or multilayer material (such as fiberglass-impregnated epoxy) and contain electrical conductors. The substrates are designed with termination pads for attaching semiconductor chips, capacitors, resistors, connection leads, pins, solder balls, solder columns etc. Interconnection between buried conductor levels in ceramic substrates can be achieved through vias formed by metal paste-filled holes in the individual ceramic layers (called greensheets) formed prior to lamination, which, upon sintering will become a sintered dense metal interconnection of metal based conductor. In the case of organic substrates, interconnection between conductor levels is by, for example, plated through hole vias.
The termination pads are often multi-layered stacks of metallization and are conventionally produced with multiple screenings, with the underlying layer being screened and dried before application of another mask and screening and drying of the next layer. Greenstein U.S. Pat. No. 4,025,669, Siuta U.S. Pat. No. 5,202,153, and Knickerbocker et al. U.S. Pat. No. 5,293,504, the disclosures of which are incorporated by reference herein, are examples where multiple screenings have been utilized to obtain either a thicker layer or a multiple layer stack of metallization.
While the prior art shows the individual layers of the stack to be perfectly aligned with every other layer in the stack, the reality is very far from this ideal case. For example, Natarajan et al. U.S. Pat. No. 5,639,562, the disclosure of which is incorporated by reference herein, shows a two layer composite metal pad with both layers perfectly aligned.
Gaynes et al. U.S. Pat. No. 5,565,033, the disclosure of which is incorporated by reference herein, discloses a process for making thicker layers of solder pastes and conductive adhesives. Gaynes et al. recognizes the disadvantages of multiple screenings as contamination between successively screened layers and the time associated with two passes through screening and drying.
In practice, the individual layers may be shifted from the layer above or below it. Mitani et al. U.S. Pat. No. 4,324,815, the disclosure of which is incorporated by reference herein, recognizes the positional error that can occur with each printing step. As disclosed in Mitani et al., the bottom layer could be made larger than the top layer so that the top layer is “captured” by the bottom layer.
However, with the trend to increasing the density of the termination pads (and reducing the spacing between adjoining termination pads), it is no longer possible to oversize the bottom layer to capture the top layer. For example, a typical pin grid array substrate has a nominal pad diameter of 1.5 mm, an interpad space of 0.3 mm and a pad tolerance of +0/−0.220 mm. This is to be compared with a typical column grid array substrate which has a nominal pad diameter of 0.800 mm, an interpad space of 0.200 mm and a pad tolerance of +/−0.050 mm.
Accordingly, it is a purpose of the present invention to have an improved process for producing multilayer stacks of metallization on a ceramic article and/or organic article.
It is another purpose of the present invention to have an improved process for producing multilayer stacks of metallization on a ceramic article and/or organic article which eliminates the positional errors which heretofore have been inherent in multiple screenings of metallization.
It is yet another purpose of the present invention to have an improved process for producing multilayer stacks of metallization for use as termination pads, lines and other features.
BRIEF SUMMARY OF THE INVENTION
One aspect of the invention relates to a method of forming a multi-layer feature on an electronic substrate article, the method comprising the steps of:
a. placing a screening mask having at least one aperture over the electronic substrate article;
b. screening a first paste through the at least one aperture of the screening mask to form a first layer of the multi-layer feature;
c. screening a second paste through the same at least one aperture of the same screening mask used in the first screening step and onto the first paste to form a second layer of the multi-layer feature in alignment with the first layer of the multi-layer feature, wherein the screening mask has not been moved between the two screening steps; and
d. removing the screening mask.
A second aspect of the invention relates to a multi-layer feature structure on an electronic substrate article comprising:
an electronic substrate article; and
a multi-layer feature structure comprising:
a first portion adjacent to the electronic substrate article; and
a second portion having a bottom and a periphery wherein the first portion contacts the bottom, and surrounds the periphery of, the second portion so that the second portion is captured by the first portion.
REFERENCES:
patent: 4025669 (1977-05-01), Greenstein
patent: 4324815 (1982-04-01), Mitani et al.
patent: 5202153 (1993-04-01), Siuta
patent: 5293504 (1994-03-01), Knickerbocker et al.
patent: 5393696 (1995-02-01), Koh et al.
patent: 5565033 (1996-10-01), Gaynes et al.
patent: 5639562 (1997-06-01), Natarajan et al.
patent: 5699733 (1997-12-01), Chang et al.
Blazick James M.
Cropp Michael E.
Humenik James N.
Leino Gerald H.
Nayak Jawahar P.
Blecker Ira D.
International Business Machines - Corporation
Talbot Brian K.
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