Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-01-04
2005-01-04
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S267000
Reexamination Certificate
active
06838344
ABSTRACT:
The invention proposes to simplify fabrication of the twin MONOS memory array. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention by adding only three additional mask levels. Conventional floating gate devices need ten or more extra masks. In the present invention, the unique twin MONOS process steps can be inserted into the standard CMOS process flow without any parameter modifications. The present invention also achieves increased endurance by means of reducing the widths of the sidewall control gate and underlying nitride storage region.
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E. Suzuki et al., “A Low-Voltage Alterable EEPROM with Metal-Oxide-Nitride-Oxide-Semiconductor (MONOS) Structures”, IEEE Transaction on Electron Devices, vol. ed-30, Feb. 1983, pp. 122-128.
Ogura Seiki
Saito Tomoya
Satoh Kimihiro
Ackerman Stephen B.
Halo LSI, Inc.
Le Thao P.
Nelms David
Pike Rosemary L. S.
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