Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-12-05
2006-12-05
Chaudhari, Chandra (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S525000, C257SE21618
Reexamination Certificate
active
07144782
ABSTRACT:
Various methods of fabricating halo regions are disclosed. In one aspect, a method of manufacturing is provided that includes forming a symmetric transistor gate and an asymmetric transistor gate on a substrate. The symmetric and asymmetric transistor gates are substantially perpendicular. A mask is formed on the substrate with a first opening and a second opening. The first opening is sized to enable implantation of first and second halo regions beneath the symmetric transistor gate. The second opening is sized to enable implantation of a third halo region beneath and on one but not both sides of the asymmetric gate. The first and second halo regions are formed beneath the first gate by implanting through the first opening toward opposite sides of the symmetric gate. The third halo region is formed beneath and proximate one but not both sides of the asymmetric transistor gate by implanting through the second opening.
REFERENCES:
patent: 5227321 (1993-07-01), Lee et al.
patent: 5580804 (1996-12-01), Joh
patent: 6030871 (2000-02-01), Eitan
patent: 6114211 (2000-09-01), Fulford et al.
patent: 6489223 (2002-12-01), Hook et al.
patent: 6566204 (2003-05-01), Wang et al.
patent: 6620679 (2003-09-01), Tzeng et al.
patent: 6747325 (2004-06-01), Shih
patent: 6784062 (2004-08-01), Cho et al.
patent: 6828202 (2004-12-01), Horch
patent: 2003/0032231 (2003-02-01), Efland et al.
U.S. Appl. No. 10/693,016, filed Oct. 24, 2003, Goad et al.
U.S. Appl. No. 10/790,939, filed Mar. 1, 2004, Sultan et al.
Stanley Wolf and Richard N. Tauber;Silicon Processing for the VLSI Era, vol. 3—The Submicron MOSFET; pp. 226-232, 240, 309-311 and 621-622; 1995.
Terence B. Hook et al.;High-Performance Logic and High-Gain Analog CMOS Transistors Formed by a Shadow-Mask Technique With a Single Implant Step; IEEE Transactions on Electron Devices, vol. 49, No. 9, Sep. 2002; pp. 1623-1627.
Advanced Micro Devices , Inc.
Chaudhari Chandra
Honeycutt Timothy M.
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